diff options
| author | Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> | 2021-09-15 13:01:55 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-02 11:48:34 +0000 |
| commit | f4b71734b266b5cf276e7bd3b0de45553a0728bd (patch) | |
| tree | 85e45203fb6a32dc86f527c74ef9c9f4ae9d369e /src/soc/mediatek/common/include | |
| parent | 38abbdab71e6bf275c9c49748f1830576ddb2f22 (diff) | |
soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
1. The original algorithm for I2C speed cannot always make the
timing meet I2C specification so a new algorithm is introduced
to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
the original implementation was fixed at fast mode (400Khz).
So the mtk_i2c_bus_init is now also taking an extra speed
parameter.
There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1
BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
at 100/300/400/500/800/1000Khz.
Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/common/include')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/i2c_common.h | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index d2da27ef4c..72ec46a093 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -3,6 +3,8 @@ #ifndef MTK_COMMON_I2C_H #define MTK_COMMON_I2C_H +#include <device/i2c.h> + /* I2C DMA Registers */ struct mt_i2c_dma_regs { uint32_t dma_int_flag; @@ -84,7 +86,6 @@ enum { }; /* I2C Status Code */ - enum { I2C_OK = 0x0000, I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, @@ -95,11 +96,51 @@ enum { I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 }; +struct mtk_i2c_ac_timing { + u16 htiming; + u16 ltiming; + u16 hs; + u16 ext; + u16 inter_clk_div; + u16 scl_hl_ratio; + u16 hs_scl_hl_ratio; + u16 sta_stop; + u16 hs_sta_stop; + u16 sda_timing; +}; + struct mtk_i2c { struct mt_i2c_regs *i2c_regs; struct mt_i2c_dma_regs *i2c_dma_regs; + struct mtk_i2c_ac_timing ac_timing; uint32_t mt_i2c_flag; }; +#define I2C_TIME_CLR_VALUE 0x0000 +#define MAX_SAMPLE_CNT_DIV 8 +#define MAX_STEP_CNT_DIV 64 +#define MAX_HS_STEP_CNT_DIV 8 +#define I2C_TIME_DEFAULT_VALUE 0x0083 +#define I2C_STANDARD_MODE_BUFFER (1000 / 3) +#define I2C_FAST_MODE_BUFFER (300 / 3) +#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) + +/* + * struct i2c_spec_values: + * @min_low_ns: min LOW period of the SCL clock + * @min_su_sta_ns: min set-up time for a repeated START condition + * @max_hd_dat_ns: max data hold time + * @min_su_dat_ns: min data set-up time + */ +struct i2c_spec_values { + uint32_t min_low_ns; + uint32_t min_su_sta_ns; + uint32_t max_hd_dat_ns; + uint32_t min_su_dat_ns; +}; + extern struct mtk_i2c mtk_i2c_bus_controller[]; +const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed); +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs); + #endif |