soc/mediatek: Move the common part of PMIC drivers to common/

The PMIC drivers can be shared by MT8192 and MT8195.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ie17e01d25405b1e5119d9c70c5f7afb915daf80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

7 files changed, 486 insertions, 0 deletions

diff --git a/src/soc/mediatek/common/include/soc/mt6315.h b/src/soc/mediatek/common/include/soc/mt6315.h
new file mode 100644
index 0000000000..6925c3d24f
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/mt6315.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT6315_H__
+#define __SOC_MEDIATEK_MT6315_H__
+
+#include <soc/spmi.h>
+#include <types.h>
+
+struct mt6315_setting {
+	unsigned short addr;
+	unsigned short val;
+	unsigned short mask;
+	unsigned char shift;
+};
+
+enum {
+	MT6315_CPU = SPMI_SLAVE_6,
+	MT6315_GPU = SPMI_SLAVE_7,
+	MT6315_MAX,
+};
+
+enum {
+	MT6315_BUCK_1 = 0,
+	MT6315_BUCK_2,
+	MT6315_BUCK_3,
+	MT6315_BUCK_4,
+	MT6315_BUCK_max,
+};
+
+enum {
+	MT6315_BUCK_TOP_ELR0    = 0x1449,
+	MT6315_BUCK_TOP_ELR3    = 0x144d,
+	MT6315_BUCK_VBUCK1_DBG0 = 0x1499,
+	MT6315_BUCK_VBUCK1_DBG3 = 0x1599,
+};
+
+void mt6315_init(void);
+void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uv);
+u32 mt6315_buck_get_voltage(u32 slvid, u32 buck_id);
+void mt6315_init_setting(void);
+void mt6315_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift);
+#endif /* __SOC_MEDIATEK_MT6315_H__ */
diff --git a/src/soc/mediatek/common/include/soc/mt6359p.h b/src/soc/mediatek/common/include/soc/mt6359p.h
new file mode 100644
index 0000000000..996d2e86d9
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/mt6359p.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT6359P_H__
+#define __SOC_MEDIATEK_MT6359P_H__
+
+#include <types.h>
+
+enum {
+	PMIC_HWCID		= 0x0008,
+	PMIC_SWCID		= 0x000a,
+	PMIC_TOP_CKPDN_CON0	= 0x010c,
+	PMIC_TOP_CKHWEN_CON0	= 0x012a,
+	PMIC_TOP_RST_MISC_SET	= 0x014c,
+	PMIC_TOP_RST_MISC_CLR	= 0x014e,
+	PMIC_OTP_CON0		= 0x038a,
+	PMIC_OTP_CON8		= 0x039a,
+	PMIC_OTP_CON11		= 0x03a0,
+	PMIC_OTP_CON12		= 0x03a2,
+	PMIC_OTP_CON13		= 0x03a4,
+	PMIC_PWRHOLD		= 0x0a08,
+	PMIC_VGPU11_DBG0	= 0x15a6,
+	PMIC_VGPU11_ELR0	= 0x15b4,
+	PMIC_VS2_VOTER		= 0x18aa,
+	PMIC_VS2_VOTER_CFG	= 0x18b0,
+	PMIC_VS2_ELR0		= 0x18b4,
+	PMIC_BUCK_VPA_DLC_CON0	= 0x1918,
+	PMIC_BUCK_VPA_DLC_CON1	= 0x191a,
+	PMIC_VSRAM_PROC1_ELR	= 0x1b44,
+	PMIC_VSRAM_PROC2_ELR	= 0x1b46,
+	PMIC_VSRAM_PROC1_VOSEL1	= 0x1e90,
+	PMIC_VSRAM_PROC2_VOSEL1	= 0x1eb0,
+	PMIC_VM18_ANA_CON0	= 0x2020,
+};
+
+struct pmic_setting {
+	unsigned short addr;
+	unsigned short val;
+	unsigned short mask;
+	unsigned char shift;
+};
+
+struct pmic_efuse {
+	unsigned short efuse_bit;
+	unsigned short addr;
+	unsigned short mask;
+	unsigned char shift;
+};
+
+enum {
+	MT6359P_GPU11 = 0,
+	MT6359P_SRAM_PROC1,
+	MT6359P_SRAM_PROC2,
+	MT6359P_MAX,
+};
+
+#define VM18_VOL_REG_SHIFT  8
+#define VM18_VOL_OFFSET 600
+
+#define EFUSE_WAIT_US 5000
+#define EFUSE_BUSY 1
+
+#define EFUSE_RG_VPA_OC_FT 78
+
+void mt6359p_init(void);
+void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv);
+u32 mt6359p_buck_get_voltage(u32 buck_id);
+void mt6359p_set_vm18_voltage(u32 vm18_uv);
+u32 mt6359p_get_vm18_voltage(void);
+void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift);
+void pmic_init_setting(void);
+void pmic_lp_setting(void);
+#endif /* __SOC_MEDIATEK_MT6359P_H__ */
diff --git a/src/soc/mediatek/common/include/soc/pmif_common.h b/src/soc/mediatek/common/include/soc/pmif_common.h
new file mode 100644
index 0000000000..a8db658c06
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/pmif_common.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MEDIATEK_SOC_PMIF_COMMON__
+#define __MEDIATEK_SOC_PMIF_COMMON__
+
+#include <types.h>
+
+enum {
+	PMIF_CMD_REG_0,
+	PMIF_CMD_REG,
+	PMIF_CMD_EXT_REG,
+	PMIF_CMD_EXT_REG_LONG,
+};
+
+struct chan_regs {
+	u32 ch_send;
+	u32 wdata;
+	u32 reserved12[3];
+	u32 rdata;
+	u32 reserved13[3];
+	u32 ch_rdy;
+	u32 ch_sta;
+};
+
+struct pmif {
+	struct mtk_pmif_regs *mtk_pmif;
+	struct chan_regs *ch;
+	u32 swinf_no;
+	u32 mstid;
+	u32 pmifid;
+	void (*read)(struct pmif *arb, u32 slvid, u32 reg, u32 *data);
+	void (*write)(struct pmif *arb, u32 slvid, u32 reg, u32 data);
+	u32 (*read_field)(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift);
+	void (*write_field)(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift);
+	int (*is_pmif_init_done)(struct pmif *arb);
+};
+
+enum {
+	PMIF_SPI,
+	PMIF_SPMI,
+};
+
+enum {
+	E_IO = 1,		/* I/O error */
+	E_BUSY,			/* Device or resource busy */
+	E_NODEV,		/* No such device */
+	E_INVAL,		/* Invalid argument */
+	E_OPNOTSUPP,		/* Operation not supported on transport endpoint */
+	E_TIMEOUT,		/* Wait for idle time out */
+	E_READ_TEST_FAIL,	/* SPI read fail */
+	E_SPI_INIT_RESET_SPI,	/* Reset SPI fail */
+	E_SPI_INIT_SIDLY,	/* SPI edge calibration fail */
+};
+
+enum pmic_interface {
+	PMIF_VLD_RDY = 0,
+	PMIF_SLP_REQ,
+};
+
+DEFINE_BIT(PMIFSPI_INF_EN_SRCLKEN_RC_HW, 4)
+
+DEFINE_BIT(PMIFSPI_OTHER_INF_DXCO0_EN, 0)
+DEFINE_BIT(PMIFSPI_OTHER_INF_DXCO1_EN, 1)
+
+DEFINE_BIT(PMIFSPI_ARB_EN_SRCLKEN_RC_HW, 4)
+DEFINE_BIT(PMIFSPI_ARB_EN_DCXO_CONN, 15)
+DEFINE_BIT(PMIFSPI_ARB_EN_DCXO_NFC, 16)
+
+DEFINE_BITFIELD(PMIFSPI_SPM_SLEEP_REQ_SEL, 1, 0)
+DEFINE_BITFIELD(PMIFSPI_SCP_SLEEP_REQ_SEL, 10, 9)
+
+DEFINE_BIT(PMIFSPI_MD_CTL_PMIF_RDY, 9)
+DEFINE_BIT(PMIFSPI_MD_CTL_SRCLK_EN, 10)
+DEFINE_BIT(PMIFSPI_MD_CTL_SRVOL_EN, 11)
+
+DEFINE_BITFIELD(PMIFSPMI_SPM_SLEEP_REQ_SEL, 1, 0)
+DEFINE_BITFIELD(PMIFSPMI_SCP_SLEEP_REQ_SEL, 10, 9)
+
+DEFINE_BIT(PMIFSPMI_MD_CTL_PMIF_RDY, 9)
+DEFINE_BIT(PMIFSPMI_MD_CTL_SRCLK_EN, 10)
+DEFINE_BIT(PMIFSPMI_MD_CTL_SRVOL_EN, 11)
+
+/* External API */
+struct pmif *get_pmif_controller(int inf, int mstid);
+void pmwrap_interface_init(void);
+int mtk_pmif_init(void);
+#endif /*__MEDIATEK_SOC_PMIF_COMMON__*/
diff --git a/src/soc/mediatek/common/include/soc/pmif_spi.h b/src/soc/mediatek/common/include/soc/pmif_spi.h
new file mode 100644
index 0000000000..ead1e81705
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/pmif_spi.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_PMIF_SPI_H__
+#define __SOC_MEDIATEK_PMIF_SPI_H__
+
+#include <soc/addressmap.h>
+#include <soc/pmif.h>
+#include <types.h>
+
+struct mtk_pmicspi_mst_regs {
+	u32 reserved1[4];
+	u32 other_busy_sta_0;
+	u32 wrap_en;
+	u32 reserved2[2];
+	u32 man_en;
+	u32 man_acc;
+	u32 reserved3[3];
+	u32 mux_sel;
+	u32 reserved4[3];
+	u32 dio_en;
+	u32 rddmy;
+	u32 cslext_write;
+	u32 cslext_read;
+	u32 cshext_write;
+	u32 cshext_read;
+	u32 ext_ck_write;
+	u32 ext_ck_read;
+	u32 si_sampling_ctrl;
+};
+
+check_member(mtk_pmicspi_mst_regs, other_busy_sta_0, 0x10);
+check_member(mtk_pmicspi_mst_regs, man_en, 0x20);
+check_member(mtk_pmicspi_mst_regs, mux_sel, 0x34);
+check_member(mtk_pmicspi_mst_regs, dio_en, 0x44);
+
+static struct mtk_pmicspi_mst_regs * const mtk_pmicspi_mst = (void *)PMICSPI_MST_BASE;
+
+/* PMIC registers */
+enum {
+	PMIC_BASE             = 0x0000,
+	PMIC_SMT_CON1         = PMIC_BASE + 0x0032,
+	PMIC_DRV_CON1         = PMIC_BASE + 0x003a,
+	PMIC_FILTER_CON0      = PMIC_BASE + 0x0042,
+	PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098,
+	PMIC_RG_SPI_CON0      = PMIC_BASE + 0x0408,
+	PMIC_DEW_DIO_EN       = PMIC_BASE + 0x040c,
+	PMIC_DEW_READ_TEST    = PMIC_BASE + 0x040e,
+	PMIC_DEW_WRITE_TEST   = PMIC_BASE + 0x0410,
+	PMIC_DEW_CRC_EN       = PMIC_BASE + 0x0414,
+	PMIC_DEW_CRC_VAL      = PMIC_BASE + 0x0416,
+	PMIC_DEW_RDDMY_NO     = PMIC_BASE + 0x0424,
+	PMIC_RG_SPI_CON2      = PMIC_BASE + 0x0426,
+	PMIC_SPISLV_KEY       = PMIC_BASE + 0x044a,
+	PMIC_INT_STA          = PMIC_BASE + 0x0452,
+	PMIC_AUXADC_ADC7      = PMIC_BASE + 0x1096,
+	PMIC_AUXADC_ADC10     = PMIC_BASE + 0x109c,
+	PMIC_AUXADC_RQST0     = PMIC_BASE + 0x1108,
+};
+
+#define PMIF_SPI_HW_INF		0x307F
+#define PMIF_SPI_MD		BIT(8)
+#define PMIF_SPI_AP_SECURE	BIT(9)
+#define PMIF_SPI_AP		BIT(10)
+#define PMIF_SPI_STAUPD		BIT(14)
+#define PMIF_SPI_TSX_HW		BIT(19)
+#define PMIF_SPI_DCXO_HW	BIT(20)
+
+#define DEFAULT_SLVID	0
+
+#define PMIF_CMD_STA	BIT(2)
+#define SPIMST_STA	BIT(9)
+
+enum {
+	SPI_CLK = 0x1,
+	SPI_CSN = 0x1 << 1,
+	SPI_MOSI = 0x1 << 2,
+	SPI_MISO = 0x1 << 3,
+	SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4,
+	SPI_SMT = SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO,
+	SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4,
+};
+
+enum {
+	SLV_IO_4_MA = 0x8,
+};
+
+enum {
+	SPI_CLK_SHIFT = 0,
+	SPI_CSN_SHIFT = 4,
+	SPI_MOSI_SHIFT = 8,
+	SPI_MISO_SHIFT = 12,
+	SPI_DRIVING = SLV_IO_4_MA << SPI_CLK_SHIFT | SLV_IO_4_MA << SPI_CSN_SHIFT |
+		      SLV_IO_4_MA << SPI_MOSI_SHIFT | SLV_IO_4_MA << SPI_MISO_SHIFT,
+};
+
+enum {
+	OP_WR    = 0x1,
+	OP_CSH   = 0x0,
+	OP_CSL   = 0x1,
+	OP_OUTS  = 0x8,
+};
+
+enum {
+	DEFAULT_VALUE_READ_TEST  = 0x5aa5,
+	WRITE_TEST_VALUE         = 0xa55a,
+};
+
+enum {
+	DUMMY_READ_CYCLES = 0x8,
+};
+
+enum {
+	E_CLK_EDGE = 1,
+	E_CLK_LAST_SETTING,
+};
+
+int pmif_spi_init(struct pmif *arb);
+void pmif_spi_iocfg(void);
+#endif /* __SOC_MEDIATEK_PMIF_SPI_H__ */
diff --git a/src/soc/mediatek/common/include/soc/pmif_spmi.h b/src/soc/mediatek/common/include/soc/pmif_spmi.h
new file mode 100644
index 0000000000..142217d068
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/pmif_spmi.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_PMIF_SPMI_H__
+#define __SOC_MEDIATEK_PMIF_SPMI_H__
+
+#include <soc/addressmap.h>
+#include <soc/pmif.h>
+
+#define DEFAULT_VALUE_READ_TEST		(0x5a)
+#define DEFAULT_VALUE_WRITE_TEST	(0xa5)
+
+/* indicate which number SW channel start, by project */
+#define PMIF_SPMI_SW_CHAN	BIT(6)
+#define PMIF_SPMI_INF		0x2F7
+
+struct mtk_rgu_regs {
+	u32 reserved[36];
+	u32 wdt_swsysrst2;
+};
+check_member(mtk_rgu_regs, wdt_swsysrst2, 0x90);
+
+struct mtk_spmi_mst_reg {
+	u32 op_st_ctrl;
+	u32 grp_id_en;
+	u32 op_st_sta;
+	u32 mst_sampl;
+	u32 mst_req_en;
+	u32 reserved1[11];
+	u32 rec_ctrl;
+	u32 rec0;
+	u32 rec1;
+	u32 rec2;
+	u32 rec3;
+	u32 rec4;
+	u32 reserved2[41];
+	u32 mst_dbg;
+};
+
+check_member(mtk_spmi_mst_reg, rec_ctrl, 0x40);
+check_member(mtk_spmi_mst_reg, mst_dbg, 0xfc);
+
+#define mtk_rug	((struct mtk_rgu_regs *)RGU_BASE)
+#define mtk_spmi_mst	((struct mtk_spmi_mst_reg *)SPMI_MST_BASE)
+
+struct cali {
+	unsigned int dly;
+	unsigned int pol;
+};
+
+enum {
+	SPMI_CK_NO_DLY = 0,
+	SPMI_CK_DLY_1T,
+};
+
+enum {
+	SPMI_CK_POL_NEG = 0,
+	SPMI_CK_POL_POS,
+};
+
+enum spmi_regs {
+	SPMI_OP_ST_CTRL,
+	SPMI_GRP_ID_EN,
+	SPMI_OP_ST_STA,
+	SPMI_MST_SAMPL,
+	SPMI_MST_REQ_EN,
+	SPMI_REC_CTRL,
+	SPMI_REC0,
+	SPMI_REC1,
+	SPMI_REC2,
+	SPMI_REC3,
+	SPMI_REC4,
+	SPMI_MST_DBG
+};
+
+/* MT6315 registers */
+enum {
+	MT6315_BASE        = 0x0,
+	MT6315_READ_TEST   = MT6315_BASE + 0x9,
+	MT6315_READ_TEST_1 = MT6315_BASE + 0xb,
+};
+
+#define MT6315_DEFAULT_VALUE_READ 0x15
+
+int pmif_spmi_init(struct pmif *arb);
+int spmi_config_master(void);
+void pmif_spmi_iocfg(void);
+#endif /* __SOC_MEDIATEK_PMIF_SPMI_H__ */
diff --git a/src/soc/mediatek/common/include/soc/pmif_sw.h b/src/soc/mediatek/common/include/soc/pmif_sw.h
new file mode 100644
index 0000000000..3b3e4dfb70
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/pmif_sw.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_PMIF_SW_H__
+#define __SOC_MEDIATEK_PMIF_SW_H__
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE		0x00
+#define SWINF_FSM_REQ		0x02
+#define SWINF_FSM_WFDLE		0x04
+#define SWINF_FSM_WFVLDCLR	0x06
+#define SWINF_INIT_DONE		0x01
+
+#define GET_SWINF_0_FSM(x)	(((x) >> 1) & 0x7)
+
+enum {
+	PMIF_READ_US        = 1000,
+	PMIF_WAIT_IDLE_US   = 1000,
+};
+
+/* calibation tolerance rate, unit: 0.1% */
+enum {
+	CAL_TOL_RATE = 40,
+	CAL_MAX_VAL = 0x7F,
+};
+
+int pmif_clk_init(void);
+#endif /* __SOC_MEDIATEK_PMIF_SW_H__ */
diff --git a/src/soc/mediatek/common/include/soc/spmi.h b/src/soc/mediatek/common/include/soc/spmi.h
new file mode 100644
index 0000000000..6d6d4a7df8
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/spmi.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_SPMI_H__
+#define __SOC_MEDIATEK_SPMI_H__
+
+#include <types.h>
+
+enum spmi_master {
+	SPMI_MASTER_0,
+	SPMI_MASTER_1,
+	SPMI_MASTER_2,
+	SPMI_MASTER_3,
+};
+
+enum spmi_slave {
+	SPMI_SLAVE_0,
+	SPMI_SLAVE_1,
+	SPMI_SLAVE_2,
+	SPMI_SLAVE_3,
+	SPMI_SLAVE_4,
+	SPMI_SLAVE_5,
+	SPMI_SLAVE_6,
+	SPMI_SLAVE_7,
+	SPMI_SLAVE_8,
+	SPMI_SLAVE_9,
+	SPMI_SLAVE_10,
+	SPMI_SLAVE_11,
+	SPMI_SLAVE_12,
+	SPMI_SLAVE_13,
+	SPMI_SLAVE_14,
+	SPMI_SLAVE_15,
+	SPMI_SLAVE_MAX,
+};
+
+enum slv_type {
+	BUCK_CPU,
+	BUCK_GPU,
+	SLV_TYPE_MAX,
+};
+
+enum slv_type_id {
+	BUCK_CPU_ID,
+	BUCK_GPU_ID,
+	SLV_TYPE_ID_MAX,
+};
+
+struct spmi_device {
+	u32 slvid;
+	enum slv_type type;
+	enum slv_type_id type_id;
+};
+#endif /* __SOC_MEDIATEK_SPMI_H__ */