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| author | Shon Wang <shon.wang@quanta.corp-partner.google.com> | 2024-06-25 16:01:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-27 14:36:37 +0000 |
| commit | 2ebfb79d336c864eb93619fb2980e5b9fc90b014 (patch) | |
| tree | 8b5ccdf7bf01220c265a16d38d896cb0965d4332 /src/soc/mediatek/common/cpu_id.c | |
| parent | d5658fd7c02d590fad8d6556872143dc1e7b6ccf (diff) | |
mb/google/brask/var/bujia: Configure Serial IO UARTs Mode
This patch configures Serial IO UARTs mode as below.
UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design.
BUG=b:338917836
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/mediatek/common/cpu_id.c')
0 files changed, 0 insertions, 0 deletions