marvell: Remove 'mvmap2315' SoC

I'm pretty sure this SoC doesn't actually exist.

Change-Id: I53e268ee1795e524a2a4562d67a2b9f28af966d1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

21 files changed, 0 insertions, 3097 deletions

diff --git a/src/soc/marvell/mvmap2315/include/soc/a2bus.h b/src/soc/marvell/mvmap2315/include/soc/a2bus.h
deleted file mode 100644
index e8b3d5de58..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/a2bus.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_A2BUS_H__
-#define __SOC_MARVELL_MVMAP2315_A2BUS_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_CCU_WIN1_ALR				0x00000000
-#define MVMAP2315_CCU_WIN1_AHR				0x000007FF
-#define MVMAP2315_CCU_WIN1_UID				0x0000000B
-
-#define MVMAP2315_CCU_WIN2_ALR				0x00000000
-#define MVMAP2315_CCU_WIN2_AHR				0x000007FF
-#define MVMAP2315_CCU_WIN2_UID				0x00000020
-
-#define MVMAP2315_CCU_WIN3_ALR				0x00000800
-#define MVMAP2315_CCU_WIN3_AHR				0x00000EFF
-#define MVMAP2315_CCU_WIN3_UID				0x00000002
-
-#define MVMAP2315_CCU_WIN4_ALR				0x00008000
-#define MVMAP2315_CCU_WIN4_AHR				0x0000BFFF
-#define MVMAP2315_CCU_WIN4_UID				0x0000000B
-
-#define MVMAP2315_CCU_RGF_WIN0_ALR			0x00000010
-#define MVMAP2315_CCU_RGF_WIN0_AHR			0x000001FF
-#define MVMAP2315_CCU_RGF_WIN0_UID			0x00000006
-
-#define MVMAP2315_CCU_RGF_WIN1_ALR			0x00000200
-#define MVMAP2315_CCU_RGF_WIN1_AHR			0x000004ff
-#define MVMAP2315_CCU_RGF_WIN1_UID			0x00000003
-
-#define MVMAP2315_CCU_RGF_WIN2_ALR			0x00000500
-#define MVMAP2315_CCU_RGF_WIN2_AHR			0x0000060F
-#define MVMAP2315_CCU_RGF_WIN2_UID			0x0000000C
-
-#define MVMAP2315_CCU_RGF_WIN3_ALR			0x00000680
-#define MVMAP2315_CCU_RGF_WIN3_AHR			0x0000068F
-#define MVMAP2315_CCU_RGF_WIN3_UID			0x00000001
-
-#define MVMAP2315_CCU_RGF_WIN4_ALR			0x00000700
-#define MVMAP2315_CCU_RGF_WIN4_AHR			0x0000073F
-#define MVMAP2315_CCU_RGF_WIN4_UID			0x00000000
-
-#define MVMAP2315_CCU_RGF_WIN5_ALR			0x00000800
-#define MVMAP2315_CCU_RGF_WIN5_AHR			0x000008FF
-#define MVMAP2315_CCU_RGF_WIN5_UID			0x00000005
-
-#define MVMAP2315_CCU_RGF_WIN6_ALR			0x00000A00
-#define MVMAP2315_CCU_RGF_WIN6_AHR			0x00000FFF
-#define MVMAP2315_CCU_RGF_WIN6_UID			0x0000000F
-
-#define MVMAP2315_CCU_RGF_WIN7_ALR			0x00001000
-#define MVMAP2315_CCU_RGF_WIN7_AHR			0x000017FF
-#define MVMAP2315_CCU_RGF_WIN7_UID			0x0000000D
-
-#define MVMAP2315_CCU_WIN_ALR_ADDRLOW_SHIFT		4
-#define MVMAP2315_CCU_WIN_AHR_ADDRHIGH_SHIFT		4
-#define MVMAP2315_CCU_WIN_CR_WINTARGET_SHIFT		8
-#define MVMAP2315_CCU_CR_WINEN				BIT(0)
-#define MVMAP2315_CCU_RGF_WIN_ADDR_HI_SHIFT		19
-#define MVMAP2315_CCU_RGF_WIN_ADDR_LO_SHIFT		6
-#define MVMAP2315_CCU_RGF_WIN_UID_SHIFT			2
-#define MVMAP2315_CCU_RGF_WIN_RGFWINEN			BIT(0)
-#define MVMAP2315_CCU_WIN_CR_WINTARGET_MASK		0x7f00
-#define MVMAP2315_CCU_WIN_ALR_ADDRLOW_MASK		0xfffff0
-#define MVMAP2315_CCU_WIN_ALR_ADDRHIGH_MASK		0xfffff0
-struct mvmap2315_a2bus_ccu_regs {
-	u32 ccu_win0_cr;
-	u32 ccu_win0_scr;
-	u32 ccu_win0_alr;
-	u32 ccu_win0_ahr;
-	u32 ccu_win1_cr;
-	u32 ccu_win1_scr;
-	u32 ccu_win1_alr;
-	u32 ccu_win1_ahr;
-	u32 ccu_win2_cr;
-	u32 ccu_win2_scr;
-	u32 ccu_win2_alr;
-	u32 ccu_win2_ahr;
-	u32 ccu_win3_cr;
-	u32 ccu_win3_scr;
-	u32 ccu_win3_alr;
-	u32 ccu_win3_ahr;
-	u32 ccu_win4_cr;
-	u32 ccu_win4_scr;
-	u32 ccu_win4_alr;
-	u32 ccu_win4_ahr;
-	u32 ccu_win5_cr;
-	u32 ccu_win5_scr;
-	u32 ccu_win5_alr;
-	u32 ccu_win5_ahr;
-	u32 ccu_win6_cr;
-	u32 ccu_win6_scr;
-	u32 ccu_win6_alr;
-	u32 ccu_win6_ahr;
-	u32 ccu_win7_cr;
-	u32 ccu_win7_scr;
-	u32 ccu_win7_alr;
-	u32 ccu_win7_ahr;
-	u8 _reserved0[0x10];
-	u32 ccu_rgf_win0;
-	u32 ccu_rgf_win1;
-	u32 ccu_rgf_win2;
-	u32 ccu_rgf_win3;
-	u32 ccu_rgf_win4;
-	u32 ccu_rgf_win5;
-	u32 ccu_rgf_win6;
-	u32 ccu_rgf_win7;
-	u32 ccu_rgf_win8;
-	u32 ccu_rgf_win9;
-	u32 ccu_rgf_win10;
-	u32 ccu_rgf_win11;
-	u32 ccu_rgf_win12;
-	u32 ccu_rgf_win13;
-	u32 ccu_rgf_win14;
-	u32 ccu_rgf_win15;
-	u32 ccu_win_gcr;
-	u32 ccu_rgf_sidr0;
-	u32 ccu_rgf_sidr1;
-	u8 _reserved1[0x04];
-	u32 ccu_rar0;
-	u32 ccu_rar1;
-	u8 _reserved2[0x18];
-	u32 ccu_sl_hmr;
-	u32 ccu_sl_mimr0;
-	u32 ccu_sl_mimr1;
-	u32 ccu_sl_revid;
-	u32 ccu_sl_dtpr0;
-	u32 ccu_sl_dtpr1;
-	u32 ccu_sl_dtpr2;
-	u32 ccu_sl_dtpr3;
-	u32 ccu_sl_dtpr4;
-	u32 ccu_sl_dtpr5;
-	u32 ccu_sl_dtpr6;
-	u32 ccu_sl_dtpr7;
-	u32 ccu_sl_dtpr8;
-	u32 ccu_sl_dtpr9;
-	u32 ccu_sl_dtpr10;
-	u32 ccu_sl_dtpr11;
-	u32 ccu_sl_dtpr12;
-	u32 ccu_sl_dtpr13;
-	u32 ccu_sl_dtpr14;
-	u32 ccu_sl_dtpr15;
-	u8 _reserved3[0xb0];
-	u32 ccu_htc_cr;
-	u32 ccu_htc_sr;
-	u32 ccu_htc_mnt_cr;
-	u8 _reserved4[0x04];
-	u32 ccu_htc_acr0;
-	u32 ccu_htc_acr1;
-	u32 ccu_htc_acr2;
-	u32 ccu_htc_acr3;
-	u32 ccu_htc_acr4;
-	u32 ccu_htc_acr5;
-	u32 ccu_htc_acr6;
-	u32 ccu_htc_acr7;
-	u32 ccu_htc_acr8;
-	u32 ccu_htc_acr9;
-	u32 ccu_htc_acr10;
-	u32 ccu_htc_acr11;
-	u32 ccu_htc_acr12;
-	u32 ccu_htc_acr13;
-	u32 ccu_htc_acr14;
-	u32 ccu_htc_acr15;
-	u8 _reserved5[0x10];
-	u32 ccu_htc_aasr;
-	u32 ccu_htc_aset;
-	u32 ccu_htc_aclr;
-	u32 ccu_sft_eir0;
-	u32 ccu_sft_eir1;
-	u8 _reserved6[0x8c];
-	u32 ccu_ltc_cr;
-	u32 ccu_ltc_sr;
-	u32 ccu_ltc_hhr;
-	u32 ccu_ltc_cr1;
-	u8 _reserved7[0xe0];
-	u32 ccu_gspmu_cr;
-	u32 ccu_gspmu_sr;
-	u8 _reserved8[0x18];
-	u32 ccu_mc_cr;
-	u8 _reserved9[0x3ec];
-	u32 ccu_rgf_cr;
-	u32 ccu_rgf_scr;
-};
-
-check_member(mvmap2315_a2bus_ccu_regs, ccu_rgf_scr, 0x804);
-static struct mvmap2315_a2bus_ccu_regs * const mvmap2315_a2bus_ccu
-					= (void *)MVMAP2315_A2BUS_CCU_BASE;
-
-#define MVMAP2315_CCU_B_LTC_CR_USERDMODROB		BIT(0)
-#define MVMAP2315_CCU_B_IDACR_PRIVATEUID_SHIFT		0
-#define MVMAP2315_CCU_B_SMC_MVN_MVNENABLE		BIT(0)
-struct mvmap2315_a2bus_regs {
-	u32 ccu_b_uid;
-	u32 ccu_b_urd;
-	u32 ccu_b_sfwd;
-	u8 _reserved0[0x04];
-	u32 ccu_b_rapc;
-	u32 ccu_b_dlapc;
-	u8 _reserved1[0x08];
-	u32 ccu_b_rsc;
-	u32 ccu_b_rsu;
-	u8 _reserved2[0x08];
-	u32 ccu_b_idacr;
-	u8 _reserved3[0x0c];
-	u32 ccu_b_rsrv0;
-	u8 _reserved4[0x0c];
-	u32 ccu_dbg_ltc_cr;
-	u32 ccu_dbg_ltc_sr;
-	u8 _reserved5[0x08];
-	u32 ccu_dbg_htc_cr;
-	u32 ccu_dbg_htc_sr;
-	u8 _reserved6[0x08];
-	u32 ccu_dbg_rsu_cr;
-	u32 ccu_dbg_rsu_sr;
-	u8 _reserved7[0x08];
-	u32 ccu_dbg_smc_cr;
-	u32 ccu_dbg_smc_sr;
-	u8 _reserved8[0x98];
-	u32 ccu_b_reicr;
-	u32 ccu_b_reimr;
-	u32 ccu_b_seicr;
-	u32 ccu_b_seimr;
-	u8 _reserved9[0xd0];
-	u32 ccu_b_mpccr;
-	u32 ccu_b_pcr;
-	u32 ccu_b_drar;
-	u32 ccu_b_mpidr;
-	u32 ccu_b_pdcr;
-	u32 ccu_b_evar;
-	u32 ccu_b_l2efr;
-	u8 _reserved10[0x04];
-	u32 ccu_b_psr;
-	u32 ccu_b_mpsr;
-	u32 ccu_b_adb_cr;
-	u32 ccu_b_adb_sr;
-	u32 ccu_b_pdr_sr;
-	u32 ccu_b_pdr_cr;
-	u32 ccu_b_l2dr_sr;
-	u32 ccu_b_l2dr_cr;
-	u32 ccu_b_rvbar0;
-	u32 ccu_b_rvbar1;
-	u32 ccu_b_rvbar2;
-	u32 ccu_b_rvbar3;
-	u32 ccu_b_prcr0;
-	u32 ccu_b_prcr1;
-	u32 ccu_b_prcr2;
-	u32 ccu_b_prcr3;
-	u32 ccu_b_wrcr0;
-	u32 ccu_b_wrcr1;
-	u32 ccu_b_wrcr2;
-	u32 ccu_b_wrcr3;
-	u32 ccu_b_drcr0;
-	u32 ccu_b_drcr1;
-	u32 ccu_b_drcr2;
-	u32 ccu_b_drcr3;
-	u32 ccu_b_crcr;
-	u32 ccu_b_rcr;
-	u8 _reserved11[0x78];
-	u32 ccu_mc_rcr;
-	u32 ccu_mc_rsbr;
-	u32 ccu_mc_rtbr;
-	u32 ccu_b_smc;
-	u32 ccu_b_smc_mvn;
-	u8 _reserved12[0x2c];
-	u32 ccu_b_ltc_sr;
-	u32 ccu_b_ltc_cr;
-	u32 ccu_b_ltc_qos_ovrd;
-	u32 qos_time_seg_cr;
-	u32 qos_bw_guarantee_th;
-	u32 qos_bw_peak_th;
-	u32 qos_bw_jam_th;
-	u32 qos_regulator_out_trans_block_cr0;
-	u32 qos_prio_cr;
-	u32 qos_critical_path_cr;
-	u32 qos_regulator_out_trans_block_cr1;
-	u32 ccu_b_ltc_tc_ovrd;
-	u8 _reserved13[0x30];
-	u32 ccu_b_htc_sr;
-	u32 ccu_b_htc_prio_dl;
-	u32 ccu_b_sp_prio_mesh_lo;
-	u32 ccu_b_sp_prio_mesh_hi;
-	u32 ccu_b_sft_far_lo;
-	u32 ccu_b_sft_far_hi;
-	u32 ccu_b_htc_mnt_sr;
-};
-
-check_member(mvmap2315_a2bus_regs, ccu_b_htc_mnt_sr, 0x3b8);
-static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_banked
-				= (void *)MVMAP2315_A2BUS_BANKED_BASE;
-static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias6
-				= (void *)MVMAP2315_A2BUS_ALIAS6_BASE;
-static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias9
-				= (void *)MVMAP2315_A2BUS_ALIAS9_BASE;
-static struct mvmap2315_a2bus_regs * const mvmap2315_a2bus_alias11
-				= (void *)MVMAP2315_A2BUS_ALIAS11_BASE;
-
-void init_a2bus_config(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_A2BUS_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h
deleted file mode 100644
index c240e0f57c..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__
-#define __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__
-
-#include <stdint.h>
-
-#define MAX_DRAM_ADDRESS		0x73000000
-
-#define MVMAP2315_CBFS_BASE		0x00400000
-#define MVMAP2315_ROMSTAGE_BASE		0xE0010000
-
-#define MVMAP2315_BOOTBLOCK_CB1		0xE0009510
-#define MVMAP2315_BOOTBLOCK_CB2		0xE0009514
-
-#define MVMAP2315_PINMUX_BASE		0xE0140000
-#define MVMAP2315_TIMER0_BASE		0xE1020000
-#define MVMAP2315_GPIOF_BASE		0xE0142000
-#define MVMAP2315_GPIOG_BASE		0xE0142100
-#define MVMAP2315_GPIOH_BASE		0xE0142200
-#define MVMAP2315_WDT0_BASE		0XE1010000
-#define MVMAP2315_WDT1_BASE		0XE1020000
-#define MVMAP2315_SP_IPC_BASE		0xED0C2000
-#define MVMAP2315_MCU_MSG_BUFF_BASE	0xEE03FF8C
-
-#define MVMAP2315_A2BUS_BANKED_BASE	0xF0000000
-#define MVMAP2315_A2BUS_ALIAS6_BASE	0xF0002000
-#define MVMAP2315_A2BUS_ALIAS9_BASE	0xF0002C00
-#define MVMAP2315_A2BUS_ALIAS11_BASE	0xF0003400
-#define MVMAP2315_A2BUS_CCU_BASE	0xF0004000
-
-#define	MVMAP2315_BCM_GICD_BASE		0xE0111000
-#define MVMAP2315_BCM_GICC_BASE		0xE0112000
-
-#define MVMAP2315_MAIN_PLL_BASE		0xE0125000
-#define MVMAP2315_APMU_CLK_BASE		0xE0125400
-#define MVMAP2315_GENTIMER_BASE		0xE0137000
-#define MVMAP2315_MPMU_CLK_BASE		0xEF000800
-#define MVMAP2315_MCU_SECCONFIG_BASE	0xED600000
-#define MVMAP2315_APMU_PWRCTL_BASE	0xE012C000
-#define MVMAP2315_LCM_REGS_BASE		0xE0130000
-#define MVMAP2315_CPU_BASE		0xF0410000
-
-#define MVMAP2315_RAM_BASE		0x00000000
-#define MVMAP2315_DEVICE_BASE		0x80000000
-#define MVMAP2315_FLASH_BASE		0xFE000000
-#define MVMAP2315_LCM_BASE		0xE0000000
-#define MVMAP2315_LOWPWR_REG		0xE0002000
-
-#define MVMAP2315_MC_BASE		0xF0020000
-#define MVMAP2315_PHY0_BASE		0xF0034000
-#define MVMAP2315_PHY1_BASE		0xF0035000
-#define MVMAP2315_PHY2_BASE		0xF0036000
-#define MVMAP2315_PHY3_BASE		0xF0037000
-
-#endif /*  __SOC_MARVELL_MVMAP2315_ADDRESS_MAP_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/apmu.h b/src/soc/marvell/mvmap2315/include/soc/apmu.h
deleted file mode 100644
index b6b52fa432..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/apmu.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_APMU_H__
-#define __SOC_MARVELL_MVMAP2315_APMU_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-enum pll_t {
-	CPU_PLL = 93,
-	MC_PLL = 94,
-	MCFLC_PLL = 95,
-	A2_PLL = 96,
-	MAIN_PLL = 97,
-	GPU_PLL0 = 98,
-	GPU_PLL1 = 99,
-	MIPI_PLL = 100,
-	DISPLAY_PLL = 101,
-	APLL0 = 102,
-};
-
-enum apll_freq_t {
-	APLL_NOCHANGE = 0,
-	APLL_589P824  = 1,
-	APLL_541P9008 = 2,
-	APLL_451P584  = 3
-};
-
-enum dev_statet_t {
-	D0 = 0,
-	D1 = 1,
-	D2 = 2,
-	D3 = 3,
-	D3WAKEINT = 11
-};
-
-enum dev_t {
-	APCPU_0 = 0,
-	APCPU_L2 = 4,
-	A2 = 5,
-	MC = 6,
-	DDRPHY_0 = 7,
-	DDRPHY_1 = 8,
-	DDRPHY_2 = 9,
-	DDRPHY_3 = 10,
-	MCFLC = 11,
-	SDMMC = 50,
-	AES256 = 54,
-	AP_AXI_HS = 55,
-	AP_UART0 = 56,
-	AP_UART1 = 57,
-	AP_M2M = 65,
-	AP_APB = 66,
-	AP_GIC = 67,
-};
-
-enum clk_t {
-	M4CLK = 124,
-};
-
-enum clk_src_t {
-	SRCSEL_NO_CHANGE =  0,
-	SRCSEL_CPU_PLL =  1,
-	SRCSEL_MC_PLL =  2,
-	SRCSEL_MCFLC_PLL =  3,
-	SRCSEL_A2_PLL =  4,
-	SRCSEL_MAIN_PLL =  5,
-	SRCSEL_GPU_PLL0 =  6,
-	SRCSEL_GPU_PLL1 =  7,
-	SRCSEL_MIPI_PLL =  8,
-	SRCSEL_DISPLAY_PLL =  9,
-	SRCSEL_APLL0 = 10,
-	SRCSEL_APLL1 = 11,
-};
-
-enum clk_state_t {
-	NOCHANGE = 0,
-	GATED = 1,
-	RUNNING = 2
-};
-
-#define MVMAP2315_APMU_PWRCMDFIFO_TIMEOUT		0x5000
-#define MVMAP2315_APMU_PWRCMDFIFO_DONEIRQ		BIT(27)
-#define MVMAP2315_APMU_ISTCLR_DONE			BIT(30)
-#define MVMAP2315_APMU_ISTCLR_ERROR			BIT(31)
-
-#define MVMAP2315_APMU_OPCODE_CLKST			1
-#define MVMAP2315_APMU_OPCODE_PWRST			2
-#define MVMAP2315_APMU_OPCODE_SHIFT			28
-
-#define MVMAP2315_APMU_DEV_FREQ_SHIFT			12
-#define MVMAP2315_APMU_DEV_STATE_SHIFT			8
-#define MVMAP2315_APMU_DEV_OBJECT_SHIFT			0
-
-#define MVMAP2315_APMU_CLK_STATE_SHIFT			25
-#define MVMAP2315_APMU_CLK_DIV_SHIFT			12
-#define MVMAP2315_APMU_CLK_SOURCE_SHIFT			8
-#define MVMAP2315_APMU_CLK_OBJECT_SHIFT			0
-
-struct mvmap2315_apmu_pwrctl_regs {
-	 u32 pwrcmdfifo;
-	 u32 pwrcmdfifostatus;
-	 u8 _reserved0[0x08];
-	 u32 intstatusset;
-	 u32 intstatusclear;
-	 u32 intstatus;
-	 u8 _reserved1[0x04];
-	 u32 doneirq;
-	 u32 errorirq;
-	 u32 scratch0;
-	 u32 scratch1;
-	 u8 _reserved2[0x10];
-	 u32 pmp_spci_rx_int_status;
-	 u32 pmp_spci_rx_int_set;
-	 u32 pmp_spci_rx_int_clear;
-	 u8 _reserved3[0x04];
-	 u32 pmp_spci_tx_int_status;
-	 u32 pmp_spci_tx_int_set;
-	 u32 pmp_spci_tx_int_clear;
-	 u8 _reserved4[0xa4];
-	 u32 global_pwrstate;
-	 u8 _reserved5[0x0c];
-	 u32 a72core0_pwrstate;
-	 u8 _reserved6[0x0c];
-	 u32 a72core1_pwrstate;
-	 u8 _reserved7[0x0c];
-	 u32 a72core2_pwrstate;
-	 u8 _reserved8[0x0c];
-	 u32 a72core3_pwrstate;
-	 u8 _reserved9[0x0c];
-	 u32 a72l2_pwrstate;
-	 u8 _reserved10[0x0c];
-	 u32 a2fab_pwrstate;
-	 u8 _reserved11[0x0c];
-	 u32 mc_pwrstate;
-	 u8 _reserved12[0x0c];
-	 u32 mc_phy0_pwrstate;
-	 u8 _reserved13[0x0c];
-	 u32 mc_phy1_pwrstate;
-	 u8 _reserved14[0x0c];
-	 u32 mc_phy2_pwrstate;
-	 u8 _reserved15[0x0c];
-	 u32 mc_phy3_pwrstate;
-	 u8 _reserved16[0x0c];
-	 u32 mcflc_pwrstate;
-	 u8 _reserved17[0x0c];
-	 u32 mcflc_phy0_pwrstate;
-	 u8 _reserved18[0x0c];
-	 u32 mcflc_phy1_pwrstate;
-	 u8 _reserved19[0x0c];
-	 u32 mcflc_phy2_pwrstate;
-	 u8 _reserved20[0x0c];
-	 u32 mcflc_phy3_pwrstate;
-	 u8 _reserved21[0x0c];
-	 u32 gpu3dcore0_pwrstate;
-	 u8 _reserved22[0x0c];
-	 u32 gpu3dcore1_pwrstate;
-	 u8 _reserved23[0x0c];
-	 u32 gpu3dcore2_pwrstate;
-	 u8 _reserved24[0x0c];
-	 u32 gpu3dcore3_pwrstate;
-	 u8 _reserved25[0x0c];
-	 u32 gpu3dl2_pwrstate;
-	 u8 _reserved26[0x0c];
-	 u32 smmu_pwrstate;
-	 u8 _reserved27[0x0c];
-	 u32 vpudec_pwrstate;
-	 u8 _reserved28[0x0c];
-	 u32 jpeg_pwrstate;
-	 u8 _reserved29[0x0c];
-	 u32 decoder_pwrstate;
-	 u8 _reserved30[0x0c];
-	 u32 vpuenc_pwrstate;
-	 u8 _reserved31[0x0c];
-	 u32 vp8_pwrstate;
-	 u8 _reserved32[0x0c];
-	 u32 vp9_pwrstate;
-	 u8 _reserved33[0x0c];
-	 u32 zram_pwrstate;
-	 u8 _reserved34[0x0c];
-	 u32 gpu2d_pwrstate;
-	 u8 _reserved35[0x0c];
-	 u32 edisplay_pwrstate;
-	 u8 _reserved36[0x0c];
-	 u32 edp_phy_pwrstate;
-	 u8 _reserved37[0x0c];
-	 u32 dsi_phy0_pwrstate;
-	 u8 _reserved38[0x0c];
-	 u32 dsi_phy1_pwrstate;
-	 u8 _reserved39[0x0c];
-	 u32 display_pwrstate;
-	 u8 _reserved40[0x0c];
-	 u32 mci_x40_pwrstate;
-	 u8 _reserved41[0x0c];
-	 u32 mci_x4_phy0_pwrstate;
-	 u8 _reserved42[0x0c];
-	 u32 mci_x41_pwrstate;
-	 u8 _reserved43[0x0c];
-	 u32 mci_x4_phy1_pwrstate;
-	 u8 _reserved44[0x0c];
-	 u32 mci_x42_pwrstate;
-	 u8 _reserved45[0x0c];
-	 u32 mci_x4_phy2_pwrstate;
-	 u8 _reserved46[0x0c];
-	 u32 mci_x2_pwrstate;
-	 u8 _reserved47[0x0c];
-	 u32 mci_x2_phy_pwrstate;
-	 u8 _reserved48[0x0c];
-	 u32 mci_x10_pwrstate;
-	 u8 _reserved49[0x0c];
-	 u32 mci_x1_phy0_pwrstate;
-	 u8 _reserved50[0x0c];
-	 u32 mci_x11_pwrstate;
-	 u8 _reserved51[0x0c];
-	 u32 mci_x1_phy1_pwrstate;
-	 u8 _reserved52[0x0c];
-	 u32 mci_x12_pwrstate;
-	 u8 _reserved53[0x0c];
-	 u32 mci_x1_phy2_pwrstate;
-	 u8 _reserved54[0x0c];
-	 u32 mci_x13_pwrstate;
-	 u8 _reserved55[0x0c];
-	 u32 mci_x1_phy3_pwrstate;
-	 u8 _reserved56[0x2c];
-	 u32 sdmmc_pwrstate;
-	 u8 _reserved57[0x0c];
-	 u32 emmc_phy_pwrstate;
-	 u8 _reserved58[0x0c];
-	 u32 sdio_phy0_pwrstate;
-	 u8 _reserved59[0x0c];
-	 u32 sdio_phy1_pwrstate;
-	 u8 _reserved60[0x0c];
-	 u32 aes256_pwrstate;
-	 u8 _reserved61[0x0c];
-	 u32 ap_axi_pwrstate;
-	 u8 _reserved62[0x1c];
-	 u32 ap_uart0_pwrstate;
-	 u8 _reserved63[0x0c];
-	 u32 ap_uart1_pwrstate;
-	 u8 _reserved64[0x0c];
-	 u32 ap_ssp0_pwrstate;
-	 u8 _reserved65[0x0c];
-	 u32 ap_ssp1_pwrstate;
-	 u8 _reserved66[0x0c];
-	 u32 ap_i2c0_pwrstate;
-	 u8 _reserved67[0x0c];
-	 u32 ap_i2c1_pwrstate;
-	 u8 _reserved68[0x0c];
-	 u32 ap_i2c2_pwrstate;
-	 u8 _reserved69[0x0c];
-	 u32 ap_i2c3_pwrstate;
-	 u8 _reserved70[0x0c];
-	 u32 ap_i2c4_pwrstate;
-	 u8 _reserved71[0x0c];
-	 u32 ap_lcm_pwrstate;
-	 u8 _reserved72[0x0c];
-	 u32 ap_m2m_pwrstate;
-	 u8 _reserved73[0x0c];
-	 u32 ap_apb_pwrstate;
-	 u8 _reserved74[0x0c];
-	 u32 bcm_r4_pwrstate;
-	 u8 _reserved75[0x0c];
-	 u32 apmu_m4_pwrstate;
-	 u8 _reserved76[0x0c];
-	 u32 ap_gic_pwrstate;
-	 u8 _reserved77[0x4c];
-	 u32 cpu_pll_pwrstate;
-	 u8 _reserved78[0x0c];
-	 u32 mc_pll_pwrstate;
-	 u8 _reserved79[0x0c];
-	 u32 mcflc_pll_pwrstate;
-	 u8 _reserved80[0x0c];
-	 u32 a2_pll_pwrstate;
-	 u8 _reserved81[0x0c];
-	 u32 main_pll_pwrstate;
-	 u8 _reserved82[0x0c];
-	 u32 gpu_pll0_pwrstate;
-	 u8 _reserved83[0x0c];
-	 u32 gpu_pll1_pwrstate;
-	 u8 _reserved84[0x0c];
-	 u32 mipi_pll_pwrstate;
-	 u8 _reserved85[0x0c];
-	 u32 display_pll_pwrstate;
-	 u8 _reserved86[0x0c];
-	 u32 avs_vmain_pwrstate;
-	 u8 _reserved87[0x0c];
-	 u32 avs_vcpu_pwrstate;
-	 u8 _reserved88[0x0c];
-	 u32 avs_vgpu_pwrstate;
-	 u8 _reserved89[0x0c];
-	 u32 ap_tsene_pwrstate;
-	 u8 _reserved90[0x0c];
-	 u32 rng_pwrstate;
-	 u8 _reserved91[0x3c];
-	 u32 padgroup29_pwrstate;
-	 u8 _reserved92[0x0c];
-	 u32 padgroup30_pwrstate;
-	 u8 _reserved93[0x0c];
-	 u32 padgroup31_pwrstate;
-	 u8 _reserved94[0x0c];
-	 u32 padgroup32_pwrstate;
-	 u8 _reserved95[0x0c];
-	 u32 padgroup33_pwrstate;
-};
-
-check_member(mvmap2315_apmu_pwrctl_regs, padgroup33_pwrstate, 0x750);
-static struct mvmap2315_apmu_pwrctl_regs * const mvmap2315_apmu_pwrctl
-					= (void *)MVMAP2315_APMU_PWRCTL_BASE;
-
-#define MVMAP2315_LCM_DIRACCESS_EN		BIT(0)
-#define MVMAP2315_LCM_START_BANK		BIT(6)
-#define MVMAP2315_LCM_END_BANK			(BIT(8) | BIT(10))
-struct mvmap2315_lcm_regs {
-	 u32 lcm_scfg;
-	 u32 lcm_access;
-	 u8 _reserved0[0x08];
-	 u32 lcm_ctrl_bank_mstr_id_wr0;
-	 u32 lcm_ctrl_bank_mstr_id_wr1;
-	 u32 lcm_ctrl_bank_mstr_id_wr2;
-	 u32 lcm_ctrl_bank_mstr_id_wr3;
-	 u32 lcm_ctrl_bank_mstr_id_wr4;
-	 u32 lcm_ctrl_bank_mstr_id_wr5;
-	 u8 _reserved1[0x28];
-	 u32 lcm_ctrl_bank_mask_id_wr0;
-	 u32 lcm_ctrl_bank_mask_id_wr1;
-	 u32 lcm_ctrl_bank_mask_id_wr2;
-	 u32 lcm_ctrl_bank_mask_id_wr3;
-	 u32 lcm_ctrl_bank_mask_id_wr4;
-	 u32 lcm_ctrl_bank_mask_id_wr5;
-	 u8 _reserved2[0x28];
-	 u32 lcm_ctrl_bank_mstr_id_rd0;
-	 u32 lcm_ctrl_bank_mstr_id_rd1;
-	 u32 lcm_ctrl_bank_mstr_id_rd2;
-	 u32 lcm_ctrl_bank_mstr_id_rd3;
-	 u32 lcm_ctrl_bank_mstr_id_rd4;
-	 u32 lcm_ctrl_bank_mstr_id_rd5;
-	 u8 _reserved3[0x28];
-	 u32 lcm_ctrl_bank_mask_id_rd0;
-	 u32 lcm_ctrl_bank_mask_id_rd1;
-	 u32 lcm_ctrl_bank_mask_id_rd2;
-	 u32 lcm_ctrl_bank_mask_id_rd3;
-	 u32 lcm_ctrl_bank_mask_id_rd4;
-	 u32 lcm_ctrl_bank_mask_id_rd5;
-};
-
-check_member(mvmap2315_lcm_regs, lcm_ctrl_bank_mask_id_rd5, 0xe4);
-static struct mvmap2315_lcm_regs * const mvmap2315_lcm_regs
-					= (void *)MVMAP2315_LCM_REGS_BASE;
-
-void apmu_start(void);
-int apmu_set_pll(u32 dev, u32 state, u32 freq);
-int apmu_set_dev(u32 dev, u32 state);
-int apmu_set_clk(u32 clk, u32 state, u32 div, u32 src);
-
-#endif /* __SOC_MARVELL_MVMAP2315_APMU_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/bdb.h b/src/soc/marvell/mvmap2315/include/soc/bdb.h
deleted file mode 100644
index a3e3ca53da..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/bdb.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_BDB_H__
-#define __SOC_MARVELL_MVMAP2315_BDB_H__
-
-#include <stdint.h>
-#include <compiler.h>
-
-#define MVMAP2315_BDB_LCM_BASE		0xE0000000
-
-enum {
-	BDB_RESERVED = 0,
-	SP_RW_FIRMWARE = 1,
-	AP_RW_FIRMWARE = 2,
-	MCU_FIRMWARE = 3,
-	APMU_FIRMWARE = 4,
-	KERNEL_IMAGE = 128,
-	KERNEL_COMMAND_LINE = 129,
-	SIXTEEN_BIT_VMLINUX_HEADER = 130
-};
-
-struct bdb_header {
-	u32 struct_magic;
-	u8 struct_major_version;
-	u8 struct_minor_version;
-	u16 struct_size;
-	u64 bdb_load_address;
-	u32 bdb_size;
-	u32 signed_size;
-	u32 oem_area_0_size;
-	u8 reserved0[8];
-} __packed;
-
-struct bdb_key {
-	u32 struct_magic;
-	u8 struct_major_version;
-	u8 struct_minor_version;
-	u16 struct_size;
-	u8 hash_alg;
-	u8 sig_alg;
-	u8 reserved0[2];
-	u32 key_version;
-	char description[128];
-	u8 key_data[];
-} __packed;
-
-struct bdb_sig {
-	u32 struct_magic;
-	u8 struct_major_version;
-	u8 struct_minor_version;
-	u16 struct_size;
-	u8 hash_alg;
-	u8 sig_alg;
-	u8 reserved0[2];
-	u32 signed_size;
-	char description[128];
-	u8 sig_SOC_MARVELL_MVMAP2315_data[];
-} __packed;
-
-struct bdb_data {
-	u32 struct_magic;
-	u8 struct_major_version;
-	u8 struct_minor_version;
-	u16 struct_size;
-	u32 data_version;
-	u32 oem_area_1_size;
-	u8 num_hashes;
-	u8 hash_entry_size;
-	u8 reserved0[2];
-	u32 signed_size;
-	u8 reserved1[8];
-	char description[128];
-} __packed;
-
-struct bdb_hash {
-	u64 offset;
-	u32 size;
-	u8 partition;
-	u8 type;
-	u8 reserved0[2];
-	u64 load_address;
-	u8 digest[32];
-} __packed;
-
-struct bdb_pointer {
-	struct bdb_header *bdb_h;
-	struct bdb_key	*bdb_k;
-	u8 *bdb_oem_0;
-	struct bdb_key *sub_k;
-	struct bdb_sig *bdb_h_s;
-	struct bdb_data *bdb_d;
-	u8 *oem_1;
-	struct bdb_hash *bdb_hash;
-	struct bdb_sig *bdb_s;
-} __packed;
-
-void set_bdb_pointers(u8 *start_addr, struct bdb_pointer *bdb_in);
-struct bdb_hash *find_bdb_image(struct bdb_pointer *bdb_info, u32 image_type);
-
-#endif /* __SOC_MARVELL_MVMAP2315_BDB_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/clock.h b/src/soc/marvell/mvmap2315/include/soc/clock.h
deleted file mode 100644
index 3e06b28447..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/clock.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software;
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY;
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_CLOCK_H__
-#define __SOC_MARVELL_MVMAP2315_CLOCK_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_CLK_M_KHZ		25000
-#define MVMAP2315_GENTIMER_EN		BIT(0)
-
-struct mvmap2315_gentimer_regs {
-	u32 cntcr;
-	u32 cntsr;
-	u32 cntcvl;
-	u32 cntcvu;
-	u8 _reserved0[0x10];
-	u32 cntfid0;
-	u8 _reserved1[0xfac];
-	u32 pidr4;
-	u8 _reserved2[0x0c];
-	u32 pidr0;
-	u32 pidr1;
-	u32 pidr2;
-	u32 pidr3;
-	u32 cidr0;
-	u32 cidr1;
-	u32 cidr2;
-	u32 cidr3;
-};
-
-check_member(mvmap2315_gentimer_regs, cidr3, 0xFFC);
-static struct mvmap2315_gentimer_regs * const mvmap2315_gentimer
-					= (void *)MVMAP2315_GENTIMER_BASE;
-
-#define MVMAP2315_PLL_LOCK		BIT(0)
-#define MVMAP2315_PLL_BYPASS_EN		BIT(16)
-
-struct mvmap2315_main_pll_regs {
-	u32 rst_prediv;
-	u32 mult_postdiv;
-	u32 kvco;
-	u32 misc;
-	u32 feedback_mode_deskew;
-	u32 offset_mode;
-	u32 fixed_mode_ssc_mode;
-	u32 ssc_freq_ssc_range;
-	u32 clk_ctrl_marvell_test;
-	u32 lock_status;
-	u32 reserve_out;
-};
-
-check_member(mvmap2315_main_pll_regs, reserve_out, 0x28);
-static struct mvmap2315_main_pll_regs * const mvmap2315_pll
-					= (void *)MVMAP2315_MAIN_PLL_BASE;
-
-#define MVMAP2315_UART_CLK_EN		BIT(1)
-#define MVMAP2315_SDMMC_CLK_RSTN	BIT(0)
-#define MVMAP2315_APMU_CLK_EN		BIT(1)
-#define MVMAP2315_APMU_CLK_RSTN		BIT(0)
-struct mvmap2315_apmu_clk_regs {
-	u32 uartfracdivcfg0;
-	u8 _reserved0[0x0c];
-	u32 uartfracdivcfg1;
-	u8 _reserved1[0x0c];
-	u32 r4clkstatus;
-	u8 _reserved2[0x5c];
-	u32 busclk2x_a2_clkgenconfig;
-	u32 busclk2x_a2_clkgenstatus;
-	u8 _reserved3[0x08];
-	u32 busclk_mcix2_clkgenconfig;
-	u32 busclk_mcix2_clkgenstatus;
-	u32 busclk_mcix2_phyreset_clkgenconfig;
-	u32 busclk_mcix2_phyreset_clkgenstatus;
-	u32 busclk_mcix10_clkgenconfig;
-	u32 busclk_mcix10_clkgenstatus;
-	u32 busclk_mcix1_phyreset0_clkgenconfig;
-	u32 busclk_mcix1_phyreset0_clkgenstatus;
-	u32 busclk_mcix11_clkgenconfig;
-	u32 busclk_mcix11_clkgenstatus;
-	u32 busclk_mcix1_phyreset1_clkgenconfig;
-	u32 busclk_mcix1_phyreset1_clkgenstatus;
-	u32 busclk_mcix12_clkgenconfig;
-	u32 busclk_mcix12_clkgenstatus;
-	u32 busclk_mcix1_phyreset2_clkgenconfig;
-	u32 busclk_mcix1_phyreset2_clkgenstatus;
-	u32 busclk_mcix13_clkgenconfig;
-	u32 busclk_mcix13_clkgenstatus;
-	u32 busclk_mcix1_phyreset3_clkgenconfig;
-	u32 busclk_mcix1_phyreset3_clkgenstatus;
-	u8 _reserved4[0x10];
-	u32 busclk_aes_clkgenconfig;
-	u32 busclk_aes_clkgenstatus;
-	u32 busclk_apaonbus_hs_clkgenconfig;
-	u32 busclk_apaonbus_hs_clkgenstatus;
-	u32 busclk_a2_clkgenconfig;
-	u32 busclk_a2_clkgenstatus;
-	u8 _reserved5[0x78];
-	u32 apaonclk_clkgenconfig;
-	u32 apaonclk_clkgenstatus;
-	u32 apaonclk_apmucpu_clkgenconfig;
-	u32 apaonclk_apmucpu_clkgenstatus;
-	u32 apaonclk_sdmmc_clkgenconfig;
-	u32 apaonclk_sdmmc_clkgenstatus;
-	u8 _reserved6[0x08];
-	u32 apaonclk_m2m_clkgenconfig;
-	u32 apaonclk_m2m_clkgenstatus;
-	u32 apaonclk_apb_clkgenconfig;
-	u32 apaonclk_apb_clkgenstatus;
-	u8 _reserved7[0x50];
-	u32 bistclk_clkgenconfig;
-	u32 bistclk_clkgenstatus;
-	u32 bistclk_a2reset_clkgenconfig;
-	u32 bistclk_a2reset_clkgenstatus;
-	u32 bistclk_apcpureset_clkgenconfig;
-	u32 bistclk_apcpureset_clkgenstatus;
-	u32 bistclk_coresightreset_clkgenconfig;
-	u32 bistclk_coresightreset_clkgenstatus;
-	u32 bistclk_mcflcreset_clkgenconfig;
-	u32 bistclk_mcflcreset_clkgenstatus;
-	u8 _reserved8[0x08];
-	u32 bistclk_gpu3dreset_clkgenconfig;
-	u32 bistclk_gpu3dreset_clkgenstatus;
-	u32 bistclk_gpu3dcorereset0_clkgenconfig;
-	u32 bistclk_gpu3dcorereset0_clkgenstatus;
-	u32 bistclk_gpu3dcorereset1_clkgenconfig;
-	u32 bistclk_gpu3dcorereset1_clkgenstatus;
-	u32 bistclk_gpu3dcorereset2_clkgenconfig;
-	u32 bistclk_gpu3dcorereset2_clkgenstatus;
-	u32 bistclk_gpu3dcorereset3_clkgenconfig;
-	u32 bistclk_gpu3dcorereset3_clkgenstatus;
-	u32 bistclk_gpu2dreset_clkgenconfig;
-	u32 bistclk_gpu2dreset_clkgenstatus;
-	u32 bistclk_zramreset_clkgenconfig;
-	u32 bistclk_zramreset_clkgenstatus;
-	u32 bistclk_vpuencreset_clkgenconfig;
-	u32 bistclk_vpuencreset_clkgenstatus;
-	u32 bistclk_vpudecreset_clkgenconfig;
-	u32 bistclk_vpudecreset_clkgenstatus;
-	u32 bistclk_displayreset_clkgenconfig;
-	u32 bistclk_displayreset_clkgenstatus;
-	u32 bistclk_edisplayreset_clkgenconfig;
-	u32 bistclk_edisplayreset_clkgenstatus;
-	u8 _reserved9[0x78];
-	u32 sdmmcbaseclk_clkgenconfig;
-	u32 sdmmcbaseclk_clkgenstatus;
-	u8 _reserved10[0x08];
-	u32 cfgclk_a2_clkgenconfig;
-	u32 cfgclk_a2_clkgenstatus;
-	u8 _reserved11[0x08];
-	u32 uartclk0_clkgenconfig;
-	u32 uartclk0_clkgenstatus;
-	u8 _reserved12[0x08];
-	u32 uartclk1_clkgenconfig;
-	u32 uartclk1_clkgenstatus;
-	u8 _reserved13[0x08];
-	u32 sspclk0_clkgenconfig;
-	u32 sspclk0_clkgenstatus;
-	u8 _reserved14[0x08];
-	u32 sspclk1_clkgenconfig;
-	u32 sspclk1_clkgenstatus;
-	u8 _reserved15[0x08];
-	u32 i2cclk0_clkgenconfig;
-	u32 i2cclk0_clkgenstatus;
-	u8 _reserved16[0x08];
-	u32 i2cclk1_clkgenconfig;
-	u32 i2cclk1_clkgenstatus;
-	u8 _reserved17[0x08];
-	u32 i2cclk2_clkgenconfig;
-	u32 i2cclk2_clkgenstatus;
-	u8 _reserved18[0x08];
-	u32 i2cclk3_clkgenconfig;
-	u32 i2cclk3_clkgenstatus;
-	u8 _reserved19[0x08];
-	u32 i2cclk4_clkgenconfig;
-	u32 i2cclk4_clkgenstatus;
-};
-
-check_member(mvmap2315_apmu_clk_regs, i2cclk4_clkgenstatus, 0x3A4);
-static struct mvmap2315_apmu_clk_regs * const mvmap2315_apmu_clk
-					= (void *)MVMAP2315_APMU_CLK_BASE;
-
-#define MVMAP2315_AP_RST_EN		BIT(0)
-#define MVMAP2315_MCU_RST_EN		BIT(0)
-struct mvmap2315_mpmu_clk_regs {
-	u32 resetap;
-	u32 resetmcu;
-	u32 resetstatus;
-	u8 _reserved0[4];
-	u32 apaudiopllselect;
-	u8 _reserved1[0x0c];
-	u32 sspa_asrc_rx_clk0;
-	u32 sspa_asrc_rx_clk1;
-	u32 sspa_asrc_rx_clk2;
-	u32 sspa_asrc_tx_clk0;
-	u32 sspa_asrc_tx_clk1;
-	u32 sspa_asrc_tx_clk2;
-	u32 dmic_asrc_clk;
-	u8 _reserved2[4];
-	u32 uartfracdivcfg0;
-	u8 _reserved3[0x0c];
-	u32 uartfracdivcfg1;
-	u8 _reserved4[0xcc];
-	u32 clk32k_clkgenconfig;
-	u32 clk32k_clkgenstatus;
-	u8 _reserved5[0x08];
-	u32 cpudbgclk_clkgenconfig;
-	u32 cpudbgclk_clkgenstatus;
-	u8 _reserved6[0x08];
-	u32 m4clk_bist_clkgenconfig;
-	u32 m4clk_bist_clkgenstatus;
-	u8 _reserved7[0x08];
-	u32 bspiclk_clkgenconfig;
-	u32 bspiclk_clkgenstatus;
-	u8 _reserved8[0x08];
-	u32 dmicclk_clkgenconfig;
-	u32 dmicclk_clkgenstatus;
-	u8 _reserved9[0x48];
-	u32 sspaclk0_clkgenconfig;
-	u32 sspaclk0_clkgenstatus;
-	u32 sspaclk1_clkgenconfig;
-	u32 sspaclk1_clkgenstatus;
-	u32 sspaclk2_clkgenconfig;
-	u32 sspaclk2_clkgenstatus;
-	u8 _reserved10[0x38];
-	u32 mcuclk_clkgenconfig;
-	u32 mcuclk_clkgenstatus;
-	u8 _reserved11[0x08];
-	u32 mcuclk_cdma_clkgenconfig;
-	u32 mcuclk_cdma_clkgenstatus;
-	u8 _reserved12[0x08];
-	u32 mcuclk_bspi_clkgenconfig;
-	u32 mcuclk_bspi_clkgenstatus;
-	u8 _reserved13[0x08];
-	u32 mcuclk_owi_clkgenconfig;
-	u32 mcuclk_owi_clkgenstatus;
-	u8 _reserved14[0x08];
-	u32 mcuclk_uart0_clkgenconfig;
-	u32 mcuclk_uart0_clkgenstatus;
-	u8 _reserved15[0x08];
-	u32 mcuclk_uart1_clkgenconfig;
-	u32 mcuclk_uart1_clkgenstatus;
-	u8 _reserved16[0x08];
-	u32 mcuclk_ssp0_clkgenconfig;
-	u32 mcuclk_ssp0_clkgenstatus;
-	u8 _reserved17[0x08];
-	u32 mcuclk_ssp1_clkgenconfig;
-	u32 mcuclk_ssp1_clkgenstatus;
-	u8 _reserved18[0x08];
-	u32 mcuclk_sspa0_clkgenconfig;
-	u32 mcuclk_sspa0_clkgenstatus;
-	u8 _reserved19[0x08];
-	u32 mcuclk_sspa1_clkgenconfig;
-	u32 mcuclk_sspa1_clkgenstatus;
-	u8 _reserved20[0x08];
-	u32 mcuclk_sspa2_clkgenconfig;
-	u32 mcuclk_sspa2_clkgenstatus;
-	u8 _reserved21[0x08];
-	u32 mcuclk_dmic0_clkgenconfig;
-	u32 mcuclk_dmic0_clkgenstatus;
-	u8 _reserved22[0x08];
-	u32 mcuclk_dmic1_clkgenconfig;
-	u32 mcuclk_dmic1_clkgenstatus;
-	u8 _reserved23[0x08];
-	u32 mcuclk_dmic2_clkgenconfig;
-	u32 mcuclk_dmic2_clkgenstatus;
-	u8 _reserved24[0x08];
-	u32 mcuclk_dmic3_clkgenconfig;
-	u32 mcuclk_dmic3_clkgenstatus;
-	u8 _reserved25[0x18];
-	u32 dmic_dclk0_clkgenconfig;
-	u32 dmic_dclk0_clkgenstatus;
-	u8 _reserved26[0x08];
-	u32 dmic_dclk1_clkgenconfig;
-	u32 dmic_dclk1_clkgenstatus;
-	u8 _reserved27[0x08];
-	u32 dmic_dclk2_clkgenconfig;
-	u32 dmic_dclk2_clkgenstatus;
-	u8 _reserved28[0x08];
-	u32 dmic_dclk3_clkgenconfig;
-	u32 dmic_dclk3_clkgenstatus;
-	u8 _reserved29[0x08];
-	u32 dmic_engdetclk_clkgenconfig;
-	u32 dmic_engdetclk_clkgenstatus;
-	u8 _reserved30[0x38];
-	u32 refclk_clkgenconfig;
-	u32 refclk_clkgenstatus;
-	u8 _reserved31[0x08];
-	u32 refclk_ssp0_clkgenconfig;
-	u32 refclk_ssp0_clkgenstatus;
-	u8 _reserved32[0x08];
-	u32 refclk_ssp1_clkgenconfig;
-	u32 refclk_ssp1_clkgenstatus;
-	u8 _reserved33[0x08];
-	u32 refclk_uart0_clkgenconfig;
-	u32 refclk_uart0_clkgenstatus;
-	u8 _reserved34[0x08];
-	u32 refclk_uart1_clkgenconfig;
-	u32 refclk_uart1_clkgenstatus;
-	u8 _reserved35[0x08];
-	u32 refclk_i2c0_clkgenconfig;
-	u32 refclk_i2c0_clkgenstatus;
-	u8 _reserved36[0x08];
-	u32 refclk_i2c1_clkgenconfig;
-	u32 refclk_i2c1_clkgenstatus;
-	u8 _reserved37[0x08];
-	u32 refclk_i2c2_clkgenconfig;
-	u32 refclk_i2c2_clkgenstatus;
-	u8 _reserved38[0x08];
-	u32 refclk_i2c3_clkgenconfig;
-	u32 refclk_i2c3_clkgenstatus;
-	u8 _reserved39[0x08];
-	u32 refclk_i2c4_clkgenconfig;
-	u32 refclk_i2c4_clkgenstatus;
-	u8 _reserved40[0x08];
-	u32 refclk_i2c5_clkgenconfig;
-	u32 refclk_i2c5_clkgenstatus;
-	u8 _reserved41[0x08];
-	u32 refclk_sspa0_clkgenconfig;
-	u32 refclk_sspa0_clkgenstatus;
-	u8 _reserved42[0x08];
-	u32 refclk_sspa1_clkgenconfig;
-	u32 refclk_sspa1_clkgenstatus;
-	u8 _reserved43[0x08];
-	u32 refclk_sspa2_clkgenconfig;
-	u32 refclk_sspa2_clkgenstatus;
-	u8 _reserved44[0x08];
-	u32 tsenclk_clkgenconfig;
-	u32 tsenclk_clkgenstatus;
-	u8 _reserved45[0x08];
-	u32 ap_tsenclk_clkgenconfig;
-	u32 ap_tsenclk_clkgenstatus;
-	u8 _reserved46[0x08];
-	u32 sspa_mclk_clkgenconfig;
-	u32 sspa_mclk_clkgenstatus;
-};
-
-check_member(mvmap2315_mpmu_clk_regs, sspa_mclk_clkgenstatus, 0x484);
-static struct mvmap2315_mpmu_clk_regs * const mvmap2315_mpmu_clk
-					= (void *)MVMAP2315_MPMU_CLK_BASE;
-
-void clock_init(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_CLOCK_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/digest.h b/src/soc/marvell/mvmap2315/include/soc/digest.h
deleted file mode 100644
index e81af17e1a..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/digest.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_DIGEST_H__
-#define __SOC_MARVELL_MVMAP2315_DIGEST_H__
-
-#include <stdint.h>
-
-#define MVMAP2315_DIGEST_INIT		0xFFE00040
-#define MVMAP2315_DIGEST_SHA_HASH	0xFFE00044
-
-typedef u32 (*security_init_F)(u32 adv_ver);
-typedef u32 (*sha_hash_F)(const u8 *msg, u32 msg_len, u8 *digest,
-			  u32 digest_len);
-
-struct digest_ops {
-	security_init_F init;
-	sha_hash_F sha_hash;
-};
-
-u32 digest_init(void);
-u32 digest_sha_hash(const u8 *msg, u32 msg_len, u8 *digest, u32 digest_len);
-u32 digest_cmp(const u8 *msg, u8 *digest, u32 digest_len);
-
-#endif /* __SOC_MARVELL_MVMAP2315_DIGEST_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/flash.h b/src/soc/marvell/mvmap2315/include/soc/flash.h
deleted file mode 100644
index fc33096a02..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/flash.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_FLASH_H__
-#define __SOC_MARVELL_MVMAP2315_FLASH_H__
-
-#include <stdint.h>
-
-#define MVMAP2315_FLASH_INIT		0xFFE00084
-#define MVMAP2315_FLASH_READ		0xFFE00088
-#define MVMAP2315_FLASH_WRITE		0xFFE0008C
-#define MVMAP2315_FLASH_SHUTDOWN	0xFFE00098
-#define MVMAP2315_FLASH_SET_PARTITION	0xFFE00094
-
-#define MVMAP2315_MMC_CLK_MHZ		0x00000019
-
-enum {
-	MVMAP2315_SD = 7,
-	MVMAP2315_EMMC = 8,
-	MVMAP2315_EEPROM = 27,
-};
-
-struct flash_params {
-	u32 offset;
-	u32 buff;
-	u32 size;
-	u32 id;
-	u32 partition;
-};
-
-struct flash_ops {
-	u32 (*init)(u32 media, u32 context, u32 clock_input_mhz);
-	u32 (*read)(u32 media, u32 context, struct flash_params *);
-	u32 (*write)(u32 media, u32 context, struct flash_params *);
-	u32 (*shutdown)(u32 media, u32 context, struct flash_params *);
-	u32 (*set_partition)(u32 media, u32 context, struct flash_params *);
-};
-
-u32 flash_init(u32 media, u32 clock_input_mhz);
-u32 flash_read(u32 media, struct flash_params *flash_image_info);
-u32 flash_write(u32 media, struct flash_params *flash_image_info);
-u32 flash_shutdown(u32 media);
-u32 flash_partition(u32 media, struct flash_params *flash_image_info);
-
-#endif /* __SOC_MARVELL_MVMAP2315_FLASH_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/gic.h b/src/soc/marvell/mvmap2315/include/soc/gic.h
deleted file mode 100644
index 568065cbc7..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/gic.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __SOC_MARVELL_MVMAP2315_GIC_H__
-#define __SOC_MARVELL_MVMAP2315_GIC_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_BCM_GICC_EN0			BIT(0)
-#define MVMAP2315_BCM_GICD_FIQ_EN		BIT(3)
-struct mvmap2315_bcm_gicc_regs {
-	 u32 ctrl;
-	 u32 pmr;
-	 u32 bpr;
-	 u32 iar;
-	 u32 eoir;
-	 u32 rpr;
-	 u32 hppir;
-	 u32 abpr;
-	 u32 aiar;
-	 u32 aeoir;
-	 u32 ahppir;
-};
-
-check_member(mvmap2315_bcm_gicc_regs, ahppir, 0x28);
-static struct mvmap2315_bcm_gicc_regs * const mvmap2315_bcm_gicc
-					= (void *)MVMAP2315_BCM_GICC_BASE;
-
-#define MVMAP2315_BCM_GICD_EN0			BIT(0)
-struct mvmap2315_bcm_gicd_regs {
-	 u32 ctrl;
-	 u32 typer;
-	 u32 iidr;
-	 u8 _reserved0[0x74];
-	 u32 igroup0;
-	 u32 igroup1;
-	 u32 igroup2;
-	 u32 igroup3;
-	 u32 igroup4;
-	 u32 igroup5;
-	 u32 igroup6;
-	 u32 igroup7;
-	 u32 igroup8;
-	 u32 igroup9;
-	 u32 igroup10;
-	 u32 igroup11;
-	 u8 _reserved1[0x50];
-	 u32 isenable0;
-	 u32 isenable1;
-	 u32 isenable2;
-	 u32 isenable3;
-	 u32 isenable4;
-	 u32 isenable5;
-	 u32 isenable6;
-	 u32 isenable7;
-	 u32 isenable8;
-	 u32 isenable9;
-	 u32 isenable10;
-	 u32 isenable11;
-	 u8 _reserved2[0x50];
-	 u32 icenable0;
-	 u32 icenable1;
-	 u32 icenable2;
-	 u32 icenable3;
-	 u32 icenable4;
-	 u32 icenable5;
-	 u32 icenable6;
-	 u32 icenable7;
-	 u32 icenable8;
-	 u32 icenable9;
-	 u32 icenable10;
-	 u32 icenable11;
-	 u8 _reserved3[0x50];
-	 u32 ispendr0;
-	 u32 ispendr1;
-	 u32 ispendr2;
-	 u32 ispendr3;
-	 u32 ispendr4;
-	 u32 ispendr5;
-	 u32 ispendr6;
-	 u32 ispendr7;
-	 u32 ispendr8;
-	 u32 ispendr9;
-	 u32 ispendr10;
-	 u32 ispendr11;
-	 u8 _reserved4[0x50];
-	 u32 icpendr0;
-	 u32 icpendr1;
-	 u32 icpendr2;
-	 u32 icpendr3;
-	 u32 icpendr4;
-	 u32 icpendr5;
-	 u32 icpendr6;
-	 u32 icpendr7;
-	 u32 icpendr8;
-	 u32 icpendr9;
-	 u32 icpendr10;
-	 u32 icpendr11;
-	 u8 _reserved5[0x50];
-	 u32 isactive0;
-	 u32 isactive1;
-	 u32 isactive2;
-	 u32 isactive3;
-	 u32 isactive4;
-	 u32 isactive5;
-	 u32 isactive6;
-	 u32 isactive7;
-	 u32 isactive8;
-	 u32 isactive9;
-	 u32 isactive10;
-	 u32 isactive11;
-	 u8 _reserved6[0x50];
-	 u32 icactive0;
-	 u32 icactive1;
-	 u32 icactive2;
-	 u32 icactive3;
-	 u32 icactive4;
-	 u32 icactive5;
-	 u32 icactive6;
-	 u32 icactive7;
-	 u32 icactive8;
-	 u32 icactive9;
-	 u32 icactive10;
-	 u32 icactive11;
-	 u8 _reserved7[0x50];
-	 u32 ipriority0;
-	 u32 ipriority1;
-	 u32 ipriority2;
-	 u32 ipriority3;
-	 u32 ipriority4;
-	 u32 ipriority5;
-	 u32 ipriority6;
-	 u32 ipriority7;
-	 u32 ipriority8;
-	 u32 ipriority9;
-	 u32 ipriority10;
-	 u32 ipriority11;
-	 u32 ipriority12;
-	 u32 ipriority13;
-	 u32 ipriority14;
-	 u32 ipriority15;
-	 u32 ipriority16;
-	 u32 ipriority17;
-	 u32 ipriority18;
-	 u32 ipriority19;
-	 u32 ipriority20;
-	 u32 ipriority21;
-	 u32 ipriority22;
-	 u32 ipriority23;
-	 u32 ipriority24;
-	 u32 ipriority25;
-	 u32 ipriority26;
-	 u32 ipriority27;
-	 u32 ipriority28;
-	 u32 ipriority29;
-	 u32 ipriority30;
-	 u32 ipriority31;
-	 u32 ipriority32;
-	 u32 ipriority33;
-	 u32 ipriority34;
-	 u32 ipriority35;
-	 u32 ipriority36;
-	 u32 ipriority37;
-	 u32 ipriority38;
-	 u32 ipriority39;
-	 u32 ipriority40;
-	 u32 ipriority41;
-	 u32 ipriority42;
-	 u32 ipriority43;
-	 u32 ipriority44;
-	 u32 ipriority45;
-	 u32 ipriority46;
-	 u32 ipriority47;
-	 u32 ipriority48;
-	 u32 ipriority49;
-	 u32 ipriority50;
-	 u32 ipriority51;
-	 u32 ipriority52;
-	 u32 ipriority53;
-	 u32 ipriority54;
-	 u32 ipriority55;
-	 u32 ipriority56;
-	 u32 ipriority57;
-	 u32 ipriority58;
-	 u32 ipriority59;
-	 u32 ipriority60;
-	 u32 ipriority61;
-	 u32 ipriority62;
-	 u32 ipriority63;
-	 u32 ipriority64;
-	 u32 ipriority65;
-	 u32 ipriority66;
-	 u32 ipriority67;
-	 u32 ipriority68;
-	 u32 ipriority69;
-	 u32 ipriority70;
-	 u32 ipriority71;
-	 u32 ipriority72;
-	 u32 ipriority73;
-	 u32 ipriority74;
-	 u32 ipriority75;
-	 u32 ipriority76;
-	 u32 ipriority77;
-	 u32 ipriority78;
-	 u32 ipriority79;
-	 u32 ipriority80;
-	 u32 ipriority81;
-	 u32 ipriority82;
-	 u32 ipriority83;
-	 u32 ipriority84;
-	 u32 ipriority85;
-	 u32 ipriority86;
-	 u32 ipriority87;
-	 u32 ipriority88;
-	 u32 ipriority89;
-	 u32 ipriority90;
-	 u32 ipriority91;
-	 u32 ipriority92;
-	 u32 ipriority93;
-	 u32 ipriority94;
-	 u32 ipriority95;
-	 u8 _reserved8[0x280];
-	 u32 itargets0;
-	 u32 itargets1;
-	 u32 itargets2;
-	 u32 itargets3;
-	 u32 itargets4;
-	 u32 itargets5;
-	 u32 itargets6;
-	 u32 itargets7;
-	 u32 itargets8;
-	 u32 itargets9;
-	 u32 itargets10;
-	 u32 itargets11;
-	 u32 itargets12;
-	 u32 itargets13;
-	 u32 itargets14;
-	 u32 itargets15;
-	 u32 itargets16;
-	 u32 itargets17;
-	 u32 itargets18;
-	 u32 itargets19;
-	 u32 itargets20;
-	 u32 itargets21;
-	 u32 itargets22;
-	 u32 itargets23;
-	 u32 itargets24;
-	 u32 itargets25;
-	 u32 itargets26;
-	 u32 itargets27;
-	 u32 itargets28;
-	 u32 itargets29;
-	 u32 itargets30;
-	 u32 itargets31;
-	 u32 itargets32;
-	 u32 itargets33;
-	 u32 itargets34;
-	 u32 itargets35;
-	 u32 itargets36;
-	 u32 itargets37;
-	 u32 itargets38;
-	 u32 itargets39;
-	 u32 itargets40;
-	 u32 itargets41;
-	 u32 itargets42;
-	 u32 itargets43;
-	 u32 itargets44;
-	 u32 itargets45;
-	 u32 itargets46;
-	 u32 itargets47;
-	 u32 itargets48;
-	 u32 itargets49;
-	 u32 itargets50;
-	 u32 itargets51;
-	 u32 itargets52;
-	 u32 itargets53;
-	 u32 itargets54;
-	 u32 itargets55;
-	 u32 itargets56;
-	 u32 itargets57;
-	 u32 itargets58;
-	 u32 itargets59;
-	 u32 itargets60;
-	 u32 itargets61;
-	 u32 itargets62;
-	 u32 itargets63;
-	 u32 itargets64;
-	 u32 itargets65;
-	 u32 itargets66;
-	 u32 itargets67;
-	 u32 itargets68;
-	 u32 itargets69;
-	 u32 itargets70;
-	 u32 itargets71;
-	 u32 itargets72;
-	 u32 itargets73;
-	 u32 itargets74;
-	 u32 itargets75;
-	 u32 itargets76;
-	 u32 itargets77;
-	 u32 itargets78;
-	 u32 itargets79;
-	 u32 itargets80;
-	 u32 itargets81;
-	 u32 itargets82;
-	 u32 itargets83;
-	 u32 itargets84;
-	 u32 itargets85;
-	 u32 itargets86;
-	 u32 itargets87;
-	 u32 itargets88;
-	 u32 itargets89;
-	 u32 itargets90;
-	 u32 itargets91;
-	 u32 itargets92;
-	 u32 itargets93;
-	 u32 itargets94;
-	 u32 itargets95;
-	 u8 _reserved9[0x280];
-	 u32 icfg0;
-	 u32 icfg1;
-	 u32 icfg2;
-	 u32 icfg3;
-	 u32 icfg4;
-	 u32 icfg5;
-	 u32 icfg6;
-	 u32 icfg7;
-	 u32 icfg8;
-	 u32 icfg9;
-	 u32 icfg10;
-	 u32 icfg11;
-	 u32 icfg12;
-	 u32 icfg13;
-	 u32 icfg14;
-	 u32 icfg15;
-	 u32 icfg16;
-	 u32 icfg17;
-	 u32 icfg18;
-	 u32 icfg19;
-	 u32 icfg20;
-	 u32 icfg21;
-	 u32 icfg22;
-	 u32 icfg23;
-	 u8 _reserved10[0xa0];
-	 u32 ppisr;
-	 u32 spisr0;
-	 u32 spisr1;
-	 u32 spisr2;
-	 u32 spisr3;
-	 u32 spisr4;
-	 u32 spisr5;
-	 u32 spisr6;
-	 u32 spisr7;
-	 u32 spisr8;
-	 u32 spisr9;
-	 u32 spisr10;
-	 u8 _reserved11[0xd0];
-	 u32 nsacr0;
-	 u32 nsacr1;
-	 u32 nsacr2;
-	 u32 nsacr3;
-	 u32 nsacr4;
-	 u32 nsacr5;
-	 u32 nsacr6;
-	 u32 nsacr7;
-	 u32 nsacr8;
-	 u32 nsacr9;
-	 u32 nsacr10;
-	 u32 nsacr11;
-	 u32 nsacr12;
-	 u32 nsacr13;
-	 u32 nsacr14;
-	 u32 nsacr15;
-	 u32 nsacr16;
-	 u32 nsacr17;
-	 u32 nsacr18;
-	 u32 nsacr19;
-	 u32 nsacr20;
-	 u32 nsacr21;
-	 u8 _reserved12[0xa8];
-	 u32 sgir;
-	 u8 _reserved13[0x0c];
-	 u32 cpendsgir0;
-	 u32 cpendsgir1;
-	 u32 cpendsgir2;
-	 u32 cpendsgir3;
-	 u32 spendsgir0;
-	 u32 spendsgir1;
-	 u32 spendsgir2;
-	 u32 spendsgir3;
-};
-
-check_member(mvmap2315_bcm_gicd_regs, spendsgir3, 0xF2C);
-static struct mvmap2315_bcm_gicd_regs * const mvmap2315_bcm_gicd
-					= (void *)MVMAP2315_BCM_GICD_BASE;
-
-void enable_bcm_gic(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_GIC_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/gpio.h b/src/soc/marvell/mvmap2315/include/soc/gpio.h
deleted file mode 100644
index 93535de90f..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/gpio.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_GPIO_H__
-#define __SOC_MARVELL_MVMAP2315_GPIO_H__
-
-#include <stdint.h>
-
-#include <types.h>
-
-#define GPIO(b, i)		((gpio_t){.bank = GPIO_##b, .idx = i})
-#define GET_GPIO_PAD(gpio)	((gpio.bank * 32) + gpio.idx + 160)
-
-struct mvmap2315_gpio_regs {
-	u32 plr;
-	u32 pdr;
-	u32 psr;
-	u32 pcr;
-	u32 hripr;
-	u32 lfipr;
-	u32 isr;
-	u32 sdr;
-	u32 cdr;
-	u32 shripr;
-	u32 chripr;
-	u32 slfipr;
-	u32 clfipr;
-	u32 olr;
-	u32 dwer;
-	u32 imr;
-	u32 rev0;
-	u32 rev1;
-	u32 simr;
-	u32 cimr;
-	u32 iter0;
-	u32 iter1;
-	u32 iter2;
-	u32 iter3;
-	u32 iter4;
-	u32 iter5;
-	u32 iter6;
-	u32 iter7;
-	u32 iter8;
-	u32 iter9;
-	u32 iter10;
-	u32 iter11;
-	u32 iter12;
-	u32 iter13;
-	u32 iter14;
-	u32 iter15;
-	u32 iter16;
-	u32 iter17;
-	u32 iter18;
-	u32 iter19;
-	u32 iter20;
-	u32 iter21;
-	u32 iter22;
-	u32 iter23;
-};
-
-check_member(mvmap2315_gpio_regs, iter23, 0xac);
-
-typedef union {
-	u32 raw;
-	struct {
-		u16 port;
-		union {
-			struct {
-				u16 num : 5;
-				u16 reserved1 : 11;
-			};
-			struct {
-				u16 idx : 3;
-				u16 bank : 2;
-				u16 reserved2 : 11;
-			};
-		};
-	};
-} gpio_t;
-
-enum {
-	GPIO_F = 0,
-	GPIO_G = 1,
-	GPIO_H = 2,
-};
-
-#endif /* __SOC_MARVELL_MVMAP2315_GPIO_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/load_validate.h b/src/soc/marvell/mvmap2315/include/soc/load_validate.h
deleted file mode 100644
index ba7f808809..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/load_validate.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__
-#define __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-enum {
-	PRIMARY_BDB = 0,
-	ALTERNATE_BDB = 1,
-	RECOVERY_BDB = 2,
-};
-
-#define MVMAP2315_BDB_TYPE		(BIT(0) | BIT(1))
-struct mvmap2315_bootrom_info {
-	u32 sp_ro_status;
-	u32 flash_media;
-};
-
-struct mvmap2315_mcu_secconfig_regs {
-	u8 _reserved0[0x04];
-	u32 strap_override_sec_cfg;
-	u32 sec_mcu_cfg_sec_cfg;
-	u32 lcm_mcu_cfg_sec_cfg0;
-	u32 lcm_mcu_cfg_sec_cfg1;
-	u32 lcm_mcu_cfg_sec_cfg2;
-	u8 _reserved1[0xe8];
-	u32 dap_debug_disable;
-	u32 boot_avs_status;
-	u32 pwr_clr_in;
-	u32 pwr_clr_recovery;
-	u32 pwr_clr_bdb;
-	u32 pwr_clr_fail_a;
-	u32 pwr_clr_fail_b;
-	u32 rst_clr_dev;
-	u32 rst_clr_wp1;
-	u32 rst_clr_wp2;
-	u32 rst_clr_lp;
-	u32 boot_gpio_out;
-	u32 boot_gpio_in;
-	u32 boot_hw_lockdown_nvm;
-	u32 boot_hw_lockdown_pinmux;
-	u32 boot_callback_pointer;
-};
-
-check_member(mvmap2315_mcu_secconfig_regs, boot_callback_pointer, 0x13c);
-static struct mvmap2315_mcu_secconfig_regs * const mvmap2315_mcu_secconfig
-					= (void *)MVMAP2315_MCU_SECCONFIG_BASE;
-
-void load_and_validate(struct bdb_pointer *bdb_info, u32 image_type);
-
-#endif /* __SOC_MARVELL_MVMAP2315_LOAD_VALIDATE_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/mcu.h b/src/soc/marvell/mvmap2315/include/soc/mcu.h
deleted file mode 100644
index 99fc5f3d00..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/mcu.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_MCU_H__
-#define __SOC_MARVELL_MVMAP2315_MCU_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_MCU_MSG_OFFSET			0xCE000000
-
-enum {
-	GET_HASH = 0x0,
-	ABORT_HASH = 0x1,
-	START_HASH = 0x2,
-	SYNC_HASH = 0x3,
-};
-
-enum {
-	ABORT = 0x0,
-	FINISHED = 0x1,
-	BUSY = 0x2
-};
-
-enum {
-	MSG_READY = 1,
-	MSG_RECEIVED = 8,
-	MSG_READY_RECEIVED = 9,
-};
-
-struct sp_hash_request_msg {
-	u8 protocol_version;
-	u8 csum;
-	u16 cmd_id;
-	u8 cmd_version;
-	u8 reserved0;
-	u16 length;
-	u8 hash_subcmd;
-	u8 hash_type;
-	u8 nonce_size;
-	u8 reserved1;
-	u32 offset;
-	u32 size;
-	u8 nonce_data[64];
-};
-
-check_member(sp_hash_request_msg, nonce_data, 0x14);
-static struct sp_hash_request_msg * const mvmap2315_mcu_msg_buff
-					= (void *)MVMAP2315_MCU_MSG_BUFF_BASE;
-
-struct mcu_hash_msg {
-	u8 protocol_version;
-	u8 csum;
-	u16 result;
-	u16 length;
-	u8 status;
-	u8 type;
-	u8 digest_size;
-	u8 reserved0;
-	u32 offset;
-	u32 size;
-	u8 digest_data[64];
-};
-
-struct mcu_pwr_status_msg {
-	u8 protocol_version;
-	u8 csum;
-	u16 cmd_id;
-	u8 cmd_version;
-	u8 reserved;
-	u16 length;
-	u8 status;
-};
-
-#define MVMAP2315_IPC_IRQSET_MSGSENT			BIT(0)
-#define MVMAP2315_IPC_IRQCLR_MSGREADY			BIT(0)
-#define MVMAP2315_IPC_IRQCLR_MSGRECEIVED		BIT(3)
-#define MVMAP2315_IPC_IRQACK				BIT(3)
-#define MVMAP2315_MCU_IPC_IRQ				BIT(6)
-struct mvmap2315_ipc_regs {
-	u32 isrr;
-	u32 wdr0;
-	u32 wdr1;
-	u32 isrw;
-	u32 icr;
-	u32 iir;
-	u32 rdr0;
-	u32 rdr1;
-	u32 maj_mid_rev;
-	u32 cfg_rev;
-	u32 dummy;
-};
-
-check_member(mvmap2315_ipc_regs, dummy, 0x28);
-static struct mvmap2315_ipc_regs * const mvmap2315_sp_ipc
-					= (void *)MVMAP2315_SP_IPC_BASE;
-
-void mcu_irq(void);
-void send_mcu_msg(void *msg, u32 size);
-void *receive_mcu_msg(void);
-void sned_hash_msg(u8 subcmd);
-void *receive_hash_msg_respond(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_MCU_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/memlayout.ld b/src/soc/marvell/mvmap2315/include/soc/memlayout.ld
deleted file mode 100644
index ecac4b2c1f..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/memlayout.ld
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-#include <arch/header.ld>
-
-SECTIONS
-{
-	DRAM_START(0x00000000)
-
-#if	ENV_RAMSTAGE
-	STACK(0x00080010, 8K)
-#endif
-	POSTRAM_CBFS_CACHE(0x1C0000, 256K)
-	RAMSTAGE(0x00200000, 640K)
-	TTB(0x00300000, 1024K)
-
-	SRAM_START(0xE0000000)
-
-	REGION(BDB, 0xE0000000, 8K, 1)
-	REGION(BootROM_CB, 0xE0002000, 24K, 1)
-
-#if	ENV_BOOTBLOCK
-	STACK(0xE0008000, 2K)
-#endif
-
-#if	ENV_ROMSTAGE
-	STACK(0xE0008800, 2K)
-#endif
-
-#if	ENV_ROMSTAGE || ENV_BOOTBLOCK
-
-	TIMESTAMP(0xE0009000, 1K)
-#endif
-
-	PRERAM_CBFS_CACHE(0xE0009400, 256)
-	REGION(bootblock_CB, 0xE0009500, 256, 1)
-	PRERAM_CBMEM_CONSOLE(0xE0009600, 8K)
-	REGION(fiq_stack, 0xE000B600, 2560, 1)
-	BOOTBLOCK(0xE000C000, 16K)
-	ROMSTAGE(0xE0010000, 64K)
-	REGION(apmu, 0xE0020000, 64K, 1)
-	SRAM_END(0xE0030000)
-}
diff --git a/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h b/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h
deleted file mode 100644
index 13c2c445fd..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/mmu_operations.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__
-#define __SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__
-
-#include <stdint.h>
-
-#define MVMAP2315_FLASH_SIZE		0x02000000
-#define MVMAP2315_RAM_SIZE		0x80000000
-#define MVMAP2315_DEVICE_SIZE		0x7E000000
-#define MVMAP2315_LCM_SIZE		0x00020000
-
-void mvmap2315_mmu_init(void);
-
-#endif /*__SOC_MARVELL_MVMAP2315_MMU_OPERATIONS_H__*/
diff --git a/src/soc/marvell/mvmap2315/include/soc/nvm.h b/src/soc/marvell/mvmap2315/include/soc/nvm.h
deleted file mode 100644
index b79c5f683b..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/nvm.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __SOC_MARVELL_MVMAP2315_NVM_H__
-#define __SOC_MARVELL_MVMAP2315_NVM_H__
-
-#include <stdint.h>
-
-#define MVMAP2315_NVM_LOCKDOWN_FLAG	BIT(0)
-
-u32 nvm_init(void);
-u32 nvm_read(u32 offset, u32 *buffer, u32 size);
-u32 nvm_write(u32 offset, u32 *buffer, u32 size);
-void nvm_lockdown(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_NVM_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/pinmux.h b/src/soc/marvell/mvmap2315/include/soc/pinmux.h
deleted file mode 100644
index 9a1f8071f7..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/pinmux.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_PINMUX_H__
-#define __SOC_MARVELL_MVMAP2315_PINMUX_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define PINMUX(a, b, c, d, e, f) ((struct mvmap2315_pinmux) {		\
-				     .pad = a,				\
-				     .fun_sel = b,			\
-				     .raw_sel = c,			\
-				     .dgtb_sel = d,			\
-				     .slew = e,				\
-				     .pull_sel = f})
-
-#define MVMAP2315_PADWRAP_FUNC_SEL	(BIT(0) | BIT(1) | BIT(2))
-#define MVMAP2315_PADWRAP_RAW_SEL	BIT(3)
-#define MVMAP2315_PADWRAP_DGTB_SEL	(BIT(4) | BIT(5) | BIT(6) | BIT(7))
-#define MVMAP2315_PADWRAP_SLEW		(BIT(11) | BIT(12))
-#define MVMAP2315_PADWRAP_PD_EN		BIT(13)
-#define MVMAP2315_PADWRAP_PU_EN		BIT(14)
-
-#define MVMAP2315_PADWRAP_FUNC_SEL_SHIFT	0
-#define MVMAP2315_PADWRAP_RAW_SEL_SHIFT		3
-#define MVMAP2315_PADWRAP_DGTB_SEL_SHIFT	4
-#define MVMAP2315_PADWRAP_SLEW_SHIFT		11
-struct mvmap2315_pinmux_regs {
-	 u32 io_pad_piocfg[72];
-	 u8 _reserved0[0xee0];
-	 u32 pc_pwrdwn_g29_pwrdn;
-	 u32 pc_v18en_lvl_g29;
-	 u32 vdd3p3_1p8_g29_reg_pwrdn;
-	 u32 pc_pwrdwn_g30_pwrdn;
-	 u32 pc_v18en_lvl_g30;
-	 u32 vdd3p3_1p8_g30_reg_pwrdn;
-	 u32 pc_pwrdwn_g31_pwrdn;
-	 u32 pc_v18en_lvl_g31;
-	 u32 vdd3p3_1p8_g31_reg_pwrdn;
-	 u32 pc_pwrdwn_g32_pwrdn;
-	 u32 pc_v18en_lvl_g32;
-	 u32 vdd3p3_1p8_g32_reg_pwrdn;
-	 u32 pc_pwrdwn_g33_pwrdn;
-	 u32 pc_v18en_lvl_g33;
-	 u32 vdd3p3_1p8_g33_reg_pwrdn;
-};
-
-check_member(mvmap2315_pinmux_regs, vdd3p3_1p8_g33_reg_pwrdn, 0x1038);
-static struct mvmap2315_pinmux_regs * const mvmap2315_pinmux
-					= (void *)MVMAP2315_PINMUX_BASE;
-
-struct mvmap2315_pinmux {
-	u32 pad;
-	u32 fun_sel;
-	u32 raw_sel;
-	u32 dgtb_sel;
-	u32 slew;
-	u32 pull_sel;
-};
-
-check_member(mvmap2315_pinmux, pull_sel, 0x14);
-
-enum {
-	PULLNONE = 0,
-	PULLDOWN = 1,
-	PULLUP = 2
-};
-
-void set_pinmux(struct mvmap2315_pinmux pinmux);
-
-#endif /* __SOC_MARVELL_MVMAP2315_PINMUX_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/pmic.h b/src/soc/marvell/mvmap2315/include/soc/pmic.h
deleted file mode 100644
index 10e22b2de9..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/pmic.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_PMIC_H__
-#define __SOC_MARVELL_MVMAP2315_PMIC_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_LOWPWR_FLAG				BIT(4)
-
-#define MVMAP2315_APGENCFG_SYSBARDISABLE		BIT(1)
-#define MVMAP2315_APGENCFG_BROADCASTINNER		BIT(2)
-#define MVMAP2315_APGENCFG_BROADCASTOUTER		BIT(3)
-#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINT		BIT(4)
-#define MVMAP2315_APGENCFG_BROADCASTCACHEMAINTPOU	BIT(5)
-#define MVMAP2315_APCORECFG0_AA64NAA32			BIT(4)
-struct mvmap2315_cpu_regs {
-	u32 fuse00;
-	u32 fuse01;
-	u32 fuse02;
-	u32 fuse03;
-	u32 fuse04;
-	u32 fuse05;
-	u32 fuse06;
-	u32 fuse07;
-	u32 fuse10;
-	u32 fuse11;
-	u32 fuse12;
-	u32 fuse13;
-	u32 fuse14;
-	u32 fuse15;
-	u32 fuse16;
-	u32 fuse17;
-	u8 _reserved0[0x20];
-	u32 fuse20;
-	u32 fuse21;
-	u32 fuse22;
-	u32 fuse23;
-	u32 fuse24;
-	u32 fuse25;
-	u32 fuse26;
-	u32 fuse27;
-	u32 fuse30;
-	u32 fuse31;
-	u32 fuse32;
-	u32 fuse33;
-	u32 fuse34;
-	u32 fuse35;
-	u32 fuse36;
-	u32 fuse37;
-	u32 fuse40;
-	u32 fuse41;
-	u32 fuse42;
-	u32 fuse43;
-	u32 fuse44;
-	u32 fuse45;
-	u32 fuse46;
-	u32 fuse47;
-	u32 fuse50;
-	u32 fuse51;
-	u32 fuse52;
-	u32 fuse53;
-	u32 fuse54;
-	u32 fuse55;
-	u32 fuse56;
-	u32 fuse57;
-	u32 fuse60;
-	u32 fuse61;
-	u32 fuse62;
-	u32 fuse63;
-	u32 fuse64;
-	u32 fuse65;
-	u32 fuse66;
-	u32 fuse67;
-	u32 fuse70;
-	u32 fuse71;
-	u32 fuse72;
-	u32 fuse73;
-	u32 fuse74;
-	u32 fuse75;
-	u32 fuse76;
-	u32 fuse77;
-	u32 fuse80;
-	u32 fuse81;
-	u32 fuse82;
-	u32 fuse83;
-	u32 fuse84;
-	u32 fuse85;
-	u32 fuse86;
-	u32 fuse87;
-	u32 fuse90;
-	u32 fuse91;
-	u32 fuse92;
-	u32 fuse93;
-	u32 fuse94;
-	u32 fuse95;
-	u32 fuse96;
-	u32 fuse97;
-	u32 fuse100;
-	u32 fuse101;
-	u32 fuse102;
-	u32 fuse103;
-	u32 fuse104;
-	u32 fuse105;
-	u32 fuse106;
-	u32 fuse107;
-	u32 fuse110;
-	u32 fuse111;
-	u32 fuse112;
-	u32 fuse113;
-	u32 fuse114;
-	u32 fuse115;
-	u32 fuse116;
-	u32 fuse117;
-	u32 fuse120;
-	u32 fuse121;
-	u32 fuse122;
-	u32 fuse123;
-	u32 fuse124;
-	u32 fuse125;
-	u32 fuse126;
-	u32 fuse127;
-	u32 fuse130;
-	u32 fuse131;
-	u32 fuse132;
-	u32 fuse133;
-	u32 fuse134;
-	u32 fuse135;
-	u32 fuse136;
-	u32 fuse137;
-	u32 fuse140;
-	u32 fuse141;
-	u32 fuse142;
-	u32 fuse143;
-	u32 fuse144;
-	u32 fuse145;
-	u32 fuse146;
-	u32 fuse147;
-	u32 fuse150;
-	u32 fuse151;
-	u32 fuse152;
-	u32 fuse153;
-	u32 fuse154;
-	u32 fuse155;
-	u32 fuse156;
-	u32 fuse157;
-	u32 apgencfg;
-	u32 apcorecfg0;
-	u32 apcorecfg1;
-	u32 apcorecfg2;
-	u32 apcorecfg3;
-	u32 rvbaraddr_low0;
-	u32 rvbaraddr_low1;
-	u32 rvbaraddr_low2;
-	u32 rvbaraddr_low3;
-	u8 _reserved1[0x10];
-	u32 rvbaraddr_high0;
-	u32 rvbaraddr_high1;
-	u32 rvbaraddr_high2;
-	u32 rvbaraddr_high3;
-	u32 highvecremap;
-};
-
-check_member(mvmap2315_cpu_regs, highvecremap, 0x264);
-static struct mvmap2315_cpu_regs * const mvmap2315_cpu
-					= (void *)MVMAP2315_CPU_BASE;
-
-enum boot_options {
-	NO_BOOT = 0,
-	CHARGING_SCREEN = 1,
-	FULL_BOOT = 2
-};
-
-void no_boot(void);
-void full_boot(void);
-void charging_screen(void);
-void mcu_start(void);
-void ap_start(void *entry);
-u32 get_boot_path(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_PMIC_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/reset.h b/src/soc/marvell/mvmap2315/include/soc/reset.h
deleted file mode 100644
index 348c9083ea..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/reset.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __SOC_MARVELL_MVMAP2315_RESET_H__
-#define __SOC_MARVELL_MVMAP2315_RESET_H__
-
-#include <stdint.h>
-
-void mvmap2315_reset(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_RESET_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/sdram.h b/src/soc/marvell/mvmap2315/include/soc/sdram.h
deleted file mode 100644
index 3c67ac38d4..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/sdram.h
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __SOC_MARVELL_MVMAP2315_SDRAM_H__
-#define __SOC_MARVELL_MVMAP2315_SDRAM_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-struct mvmap2315_sdram_params {
-	u32  dphy_params[100];
-	u32  mc_params[122];
-};
-
-struct mvmap2315_dphy_regs {
-	u32 dphy_id;
-	u32 dphy_phy_user0;
-	u8 reserved0[0x04];
-	u32 dphy_flag;
-	u32 dphy_dq_pad_ctrl0;
-	u32 dphy_dq_pad_ctrl2;
-	u8 reserved1[0x08];
-	u32 dphy_ck_pad_ctrl0;
-	u32 dphy_ck_pad_ctrl2;
-	u8 reserved2[0x04];
-	u32 dphy_ck_pad_ctrl6;
-	u32 dphy_adcm_pad_ctrl0;
-	u32 dphy_adcm_pad_ctrl2;
-	u8 reserved3[0x28];
-	u32 dphy_dfi_ctrl0;
-	u32 dphy_dfi_ctrl2;
-	u32 dphy_dfi_ctrl4;
-	u32 dphy_dfi_ctrl6;
-	u32 dphy_wl_ctrl0;
-	u8 reserved4[0x0c];
-	u32 dphy_qsg_ctrl0;
-	u8 reserved5[0x0c];
-	u32 dphy_qsg_d_ctrl0;
-	u8 reserved6[0x1c];
-	u32 dphy_rdlvl_ctrl0;
-	u8 reserved7[0x0c];
-	u32 dphy_cal_pad_ctrl0;
-	u32 dphy_cal_pad_ctrl2;
-	u32 dphy_dll_vreg_ctrl;
-	u32 dphy_vref_ctrl0;
-	u32 dphy_cat_ctrl0;
-	u32 dphy_cat_stat0;
-	u32 dphy_cat_stat2;
-	u32 dphy_cat_stat4;
-	u32 dphy_cat_marg0;
-	u32 dphy_cat_marg2;
-	u32 dphy_cat_marg4;
-	u32 dphy_cat_mctl;
-	u32 dphy_apb_ctrl0;
-	u32 dphy_monitor;
-	u32 dphy_adcm_reserve;
-	u8 reserved8[0x04];
-	u32 dphy_dll_ctrl_0;
-	u8 reserved9[0x1c];
-	u32 dphy_dll_ctrl0;
-	u32 dphy_dll_ctrl2;
-	u8 reserved10[0x04];
-	u32 dphy_dll_tst_out;
-	u8 reserved11[0x10];
-	u32 dphy_dq_dly_ctrl0;
-	u8 reserved12[0x1c];
-	u32 dphy_qs_dly_ctrl0;
-	u8 reserved13[0x5c];
-	u32 dphy_dll_phrng0;
-	u8 reserved14[0x3c];
-	u32 dphy_ca_dly_ctrl0;
-	u32 dphy_ca_dly_ctrl1;
-	u32 dphy_ca_dly_ctrl2;
-	u32 dphy_ca_dly_ctrl3;
-	u32 dphy_ca_dly_ctrl4;
-	u8 reserved15[0x0c];
-	u32 dphy_ad0_dly_ctrl;
-	u8 reserved16[0x0c];
-	u32 dphy_ck_dly_ctrl0;
-	u8 reserved17[0x5c];
-	u32 dphy_qsg_d_out0;
-	u8 reserved18[0x12c];
-	u32 dphy_lb_ctrl0;
-	u32 dphy_lb_sts0;
-	u32 dphy_lb_cnt0;
-	u8 reserved19[0x04];
-	u32 dphy_lb_seed0;
-	u32 dphy_lb_seed2;
-};
-
-check_member(mvmap2315_dphy_regs, dphy_lb_seed2, 0x3D4);
-static struct mvmap2315_dphy_regs * const mvmap2315_dphy0
-					= (void *)MVMAP2315_PHY0_BASE;
-static struct mvmap2315_dphy_regs * const mvmap2315_dphy1
-					= (void *)MVMAP2315_PHY1_BASE;
-static struct mvmap2315_dphy_regs * const mvmap2315_dphy2
-					= (void *)MVMAP2315_PHY2_BASE;
-static struct mvmap2315_dphy_regs * const mvmap2315_dphy3
-					= (void *)MVMAP2315_PHY3_BASE;
-
-#define MVMAP2315_MC_DRAM_READY			BIT(0)
-struct mvmap2315_mc_regs {
-	u32 mc_id;
-	u32 mc_status_ch0;
-	u32 dram_status;
-	u8 reserved0[0x04];
-	u32 mc_status_ch1;
-	u32 mc_status_ch2;
-	u32 mc_status_ch3;
-	u32 dram_status1;
-	u32 user_command_0;
-	u32 user_command_1;
-	u32 user_command_2;
-	u32 user_command_3;
-	u8 reserved1[0x10];
-	u32 sram_control;
-	u32 mc_control_0;
-	u32 exclusive_monitor;
-	u32 ras_control;
-	u32 spool_control;
-	u32 mc_pwr_ctl;
-	u32 wb_control;
-	u32 cat_priority_ctl;
-	u32 rob_control;
-	u32 rdp_control;
-	u32 axi_port_control;
-	u32 wb_control1;
-	u32 regtable_control;
-	u32 regtable_data_0;
-	u32 regtable_data_1;
-	u32 rz_access_ctl;
-	u32 tz_range0_low;
-	u32 tz_range0_high;
-	u32 tz_range1_low;
-	u32 tz_range1_high;
-	u32 tz_range2_low;
-	u32 tz_range2_high;
-	u32 tz_range3_low;
-	u32 tz_range3_high;
-	u32 tz_range4_low;
-	u32 tz_range4_high;
-	u32 tz_range5_low;
-	u32 tz_range5_high;
-	u32 tz_range6_low;
-	u32 tz_range6_high;
-	u32 tz_range7_low;
-	u32 tz_range7_high;
-	u32 tz_range8_low;
-	u32 tz_range8_high;
-	u32 tz_range9_low;
-	u32 tz_range9_high;
-	u32 tz_range10_low;
-	u32 tz_range10_high;
-	u32 tz_range11_low;
-	u32 tz_range11_high;
-	u32 tz_range12_low;
-	u32 tz_range12_high;
-	u32 tz_range13_low;
-	u32 tz_range13_high;
-	u32 tz_range14_low;
-	u32 tz_range14_high;
-	u32 tz_range15_low;
-	u32 tz_range15_high;
-	u32 pc_config0;
-	u32 pc_config1;
-	u32 pc_status;
-	u32 pc_control;
-	u32 pc0;
-	u32 pc1;
-	u32 pc2;
-	u32 pc3;
-	u32 pc4;
-	u32 pc5;
-	u32 pc6;
-	u32 pc7;
-	u8 reserved2[0x10];
-	u32 isr;
-	u32 ier;
-	u8 reserved3[0x08];
-	u32 adc_err_id;
-	u32 adc_err_adr_l;
-	u32 adc_err_adr_h;
-	u8 reserved4[0x04];
-	u32 am_period;
-	u32 am_th;
-	u8 reserved5[0x08];
-	u32 am2_period;
-	u32 am2_low_th;
-	u32 am2_high_th;
-	u32 am2_busy_cycle;
-	u32 rpp_starvation_control;
-	u32 bw_allocation_tc_window0;
-	u32 bw_allocation_tc_window1;
-	u32 bw_allocation_tc_window2;
-	u32 bw_allocation_tc_window3;
-	u32 bw_allocation_tc_window4;
-	u32 bw_allocation_tc_window5;
-	u32 bw_allocation_tc_window6;
-	u32 bw_allocation_tc_window7;
-	u32 bw_allocation_tc_window8;
-	u32 bw_allocation_tc_window9;
-	u32 bw_allocation_tc_window10;
-	u32 bw_allocation_tc_window11;
-	u32 bw_allocation_tc_window12;
-	u32 bw_allocation_tc_window13;
-	u32 bw_allocation_tc_window14;
-	u32 bw_allocation_tc_window15;
-	u32 cat_priority_ctl_ddr4;
-	u8 reserved6[0x38];
-	u32 mmap0_low_ch0;
-	u32 mmap0_high_ch0;
-	u32 mmap1_low_ch0;
-	u32 mmap1_high_ch0;
-	u8 reserved7[0x10];
-	u32 ch0_mc_config_cs0;
-	u32 ch0_mc_config_cs1;
-	u8 reserved8[0x98];
-	u32 ch0_mc_control_1;
-	u32 ch0_mc_control_2;
-	u32 ch0_mc_control_3;
-	u32 ch0_mc_control_4;
-	u8 reserved9[0x30];
-	u32 ch0_dram_config_1;
-	u32 ch0_dram_config_2;
-	u32 ch0_dram_config_3;
-	u32 ch0_dram_config_4;
-	u32 ch0_dram_config_5_cs0;
-	u32 ch0_dram_config_5_cs1;
-	u8 reserved10[0x08];
-	u32 ch0_dram_config_6;
-	u32 ch0_dram_config_7;
-	u32 ch0_dram_config_8;
-	u32 ch0_dram_config_9;
-	u32 ch0_dram_config_10;
-	u32 ch0_dram_config_11;
-	u32 ch0_dram_config_12;
-	u8 reserved11;
-	u32 ch0_odt_control_0;
-	u32 ch0_odt_control_1;
-	u32 ch0_odt_control_2;
-	u32 ch0_odt_control_3;
-	u32 ch0_rdimm_config_0;
-	u32 ch0_rdimm_config_1;
-	u32 ch0_rdimm_config_2;
-	u32 ch0_rdimm_config_3;
-	u8 reserved12[0x10];
-	u32 ch0_mrr_data;
-	u8 reserved13[0x0c];
-	u32 ch0_ddr_init_timing_control_0;
-	u32 ch0_ddr_init_timing_control_1;
-	u32 ch0_ddr_init_timing_control_2;
-	u32 ch0_zqc_timing_0;
-	u32 ch0_zqc_timing_1;
-	u32 ch0_refresh_timing;
-	u32 ch0_selfrefresh_timing_0;
-	u32 ch0_selfrefresh_timing_1;
-	u32 ch0_powerdown_timing_0;
-	u32 ch0_powerdown_timing_1;
-	u32 ch0_mrs_timing;
-	u32 ch0_act_timing;
-	u32 ch0_precharge_timing;
-	u32 ch0_cas_ras_timing_0;
-	u32 ch0_cas_ras_timing_1;
-	u32 ch0_off_spec_timing_0;
-	u32 ch0_off_spec_timing_1;
-	u32 ch0_dram_read_timing;
-	u32 ch0_dram_ca_train_timing;
-	u8 reserved14[0x0c];
-	u32 ch0_dram_training_timing;
-	u32 ch0_rdimm_timing_0;
-	u32 ch0_rdimm_timing_1;
-	u8 reserved15[0x1c];
-	u32 mmap0_low_ch1;
-	u32 mmap0_high_ch1;
-	u32 mmap1_low_ch1;
-	u32 mmap1_high_ch1;
-	u8 reserved16[0x10];
-	u32 ch1_mc_config_cs0;
-	u32 ch1_mc_config_cs1;
-	u8 reserved17[0x98];
-	u32 ch1_mc_control_1;
-	u32 ch1_mc_control_2;
-	u32 ch1_mc_control_3;
-	u32 ch1_mc_control_4;
-	u8 reserved18[0x30];
-	u32 ch1_dram_config_1;
-	u32 ch1_dram_config_2;
-	u32 ch1_dram_config_3;
-	u32 ch1_dram_config_4;
-	u32 ch1_dram_config_5_cs0;
-	u32 ch1_dram_config_5_cs1;
-	u8 reserved19[0x08];
-	u32 ch1_dram_config_6;
-	u32 ch1_dram_config_7;
-	u32 ch1_dram_config_8;
-	u32 ch1_dram_config_9;
-	u32 ch1_dram_config_10;
-	u32 ch1_dram_config_11;
-	u32 ch1_dram_config_12;
-	u8 reserved20[0x04];
-	u32 ch1_odt_control_0;
-	u32 ch1_odt_control_1;
-	u32 ch1_odt_control_2;
-	u32 ch1_odt_control_3;
-	u32 ch1_rdimm_config_0;
-	u32 ch1_rdimm_config_1;
-	u32 ch1_rdimm_config_2;
-	u32 ch1_rdimm_config_3;
-	u8 reserved21[0x10];
-	u32 ch1_mrr_data;
-	u8 reserved22[0x0c];
-	u32 ch1_ddr_init_timing_control_0;
-	u32 ch1_ddr_init_timing_control_1;
-	u32 ch1_ddr_init_timing_control_2;
-	u32 ch1_zqc_timing_0;
-	u32 ch1_zqc_timing_1;
-	u32 ch1_refresh_timing;
-	u32 ch1_selfrefresh_timing_0;
-	u32 ch1_selfrefresh_timing_1;
-	u32 ch1_powerdown_timing_0;
-	u32 ch1_powerdown_timing_1;
-	u32 ch1_mrs_timing;
-	u32 ch1_act_timing;
-	u32 ch1_precharge_timing;
-	u32 ch1_cas_ras_timing_0;
-	u32 ch1_cas_ras_timing_1;
-	u32 ch1_off_spec_timing_0;
-	u32 ch1_off_spec_timing_1;
-	u32 ch1_dram_read_timing;
-	u32 ch1_dram_ca_train_timing;
-	u8 reserved23[0x0c];
-	u32 ch1_dram_training_timing;
-	u32 ch1_rdimm_timing_0;
-	u32 ch1_rdimm_timing_1;
-	u8 reserved24[0x1c];
-	u32 mmap0_low_ch2;
-	u32 mmap0_high_ch2;
-	u32 mmap1_low_ch2;
-	u32 mmap1_high_ch2;
-	u8 reserved25[0x10];
-	u32 ch2_mc_config_cs0;
-	u32 ch2_mc_config_cs1;
-	u8 reserved26[0x98];
-	u32 ch2_mc_control_1;
-	u32 ch2_mc_control_2;
-	u32 ch2_mc_control_3;
-	u32 ch2_mc_control_4;
-	u8 reserved27[0x30];
-	u32 ch2_dram_config_1;
-	u32 ch2_dram_config_2;
-	u32 ch2_dram_config_3;
-	u32 ch2_dram_config_4;
-	u32 ch2_dram_config_5_cs0;
-	u32 ch2_dram_config_5_cs1;
-	u8 reserved28[0x08];
-	u32 ch2_dram_config_6;
-	u32 ch2_dram_config_7;
-	u32 ch2_dram_config_8;
-	u32 ch2_dram_config_9;
-	u32 ch2_dram_config_10;
-	u32 ch2_dram_config_11;
-	u32 ch2_dram_config_12;
-	u8 reserved29[0x04];
-	u32 ch2_odt_control_0;
-	u32 ch2_odt_control_1;
-	u32 ch2_odt_control_2;
-	u32 ch2_odt_control_3;
-	u32 ch2_rdimm_config_0;
-	u32 ch2_rdimm_config_1;
-	u32 ch2_rdimm_config_2;
-	u32 ch2_rdimm_config_3;
-	u8 reserved30[0x10];
-	u32 ch2_mrr_data;
-	u8 reserved31[0x0c];
-	u32 ch2_ddr_init_timing_control_0;
-	u32 ch2_ddr_init_timing_control_1;
-	u32 ch2_ddr_init_timing_control_2;
-	u32 ch2_zqc_timing_0;
-	u32 ch2_zqc_timing_1;
-	u32 ch2_refresh_timing;
-	u32 ch2_selfrefresh_timing_0;
-	u32 ch2_selfrefresh_timing_1;
-	u32 ch2_powerdown_timing_0;
-	u32 ch2_powerdown_timing_1;
-	u32 ch2_mrs_timing;
-	u32 ch2_act_timing;
-	u32 ch2_precharge_timing;
-	u32 ch2_cas_ras_timing_0;
-	u32 ch2_cas_ras_timing_1;
-	u32 ch2_off_spec_timing_0;
-	u32 ch2_off_spec_timing_1;
-	u32 ch2_dram_read_timing;
-	u32 ch2_dram_ca_train_timing;
-	u8 reserved32[0x0c];
-	u32 ch2_dram_training_timing;
-	u32 ch2_rdimm_timing_0;
-	u32 ch2_rdimm_timing_1;
-	u8 reserved33[0x1c];
-	u32 mmap0_low_ch3;
-	u32 mmap0_high_ch3;
-	u32 mmap1_low_ch3;
-	u32 mmap1_high_ch3;
-	u8 reserved34[0x10];
-	u32 ch3_mc_config_cs0;
-	u32 ch3_mc_config_cs1;
-	u8 reserved35[0x98];
-	u32 ch3_mc_control_1;
-	u32 ch3_mc_control_2;
-	u32 ch3_mc_control_3;
-	u32 ch3_mc_control_4;
-	u8 reserved36[0x30];
-	u32 ch3_dram_config_1;
-	u32 ch3_dram_config_2;
-	u32 ch3_dram_config_3;
-	u32 ch3_dram_config_4;
-	u32 ch3_dram_config_5_cs0;
-	u32 ch3_dram_config_5_cs1;
-	u8 reserved37[0x08];
-	u32 ch3_dram_config_6;
-	u32 ch3_dram_config_7;
-	u32 ch3_dram_config_8;
-	u32 ch3_dram_config_9;
-	u32 ch3_dram_config_10;
-	u32 ch3_dram_config_11;
-	u32 ch3_dram_config_12;
-	u8 reserved38[0x04];
-	u32 ch3_odt_control_0;
-	u32 ch3_odt_control_1;
-	u32 ch3_odt_control_2;
-	u32 ch3_odt_control_3;
-	u32 ch3_rdimm_config_0;
-	u32 ch3_rdimm_config_1;
-	u32 ch3_rdimm_config_2;
-	u32 ch3_rdimm_config_3;
-	u8 reserved39[0x10];
-	u32 ch3_mrr_data;
-	u8 reserved40[0x0c];
-	u32 ch3_ddr_init_timing_control_0;
-	u32 ch3_ddr_init_timing_control_1;
-	u32 ch3_ddr_init_timing_control_2;
-	u32 ch3_zqc_timing_0;
-	u32 ch3_zqc_timing_1;
-	u32 ch3_refresh_timing;
-	u32 ch3_selfrefresh_timing_0;
-	u32 ch3_selfrefresh_timing_1;
-	u32 ch3_powerdown_timing_0;
-	u32 ch3_powerdown_timing_1;
-	u32 ch3_mrs_timing;
-	u32 ch3_act_timing;
-	u32 ch3_precharge_timing;
-	u32 ch3_cas_ras_timing_0;
-	u32 ch3_cas_ras_timing_1;
-	u32 ch3_off_spec_timing_0;
-	u32 ch3_off_spec_timing_1;
-	u32 ch3_dram_read_timing;
-	u32 ch3_dram_ca_train_timing;
-	u8 reserved41[0x0c];
-	u32 ch3_dram_training_timing;
-	u32 ch3_rdimm_timing_0;
-	u32 ch3_rdimm_timing_1;
-	u8 reserved42[0x6c];
-	u32 test_control;
-	u8 reserved43[0x0c];
-	u32 user_trigger_ir;
-	u8 reserved44[0x08];
-	u32 training_control;
-	u32 training_pattern0;
-	u32 training_pattern1;
-	u32 training_pattern2;
-	u32 training_pattern3;
-	u32 training_pattern4;
-	u32 training_pattern5;
-	u32 training_pattern6;
-	u32 training_pattern7;
-	u32 dmi_training_pattern;
-	u8 reserved45[0x93c];
-	u32 dfi_phy_user_command_0;
-	u8 reserved46[0x0c];
-	u32 ch0_dfi_phy_control_0;
-	u32 ch0_dfi_phy_control_1;
-	u32 ch0_dfi_phy_control_2;
-	u32 ch0_dfi_phy_control_3;
-	u32 ch0_dfi_phy_ca_train;
-	u32 ch0_dfi_phy_ca_pattern;
-	u32 ch0_dfi_phy_write_dq_train;
-	u32 ch0_dfi_phy_leveling_status;
-	u8 reserved47[0x3e0];
-	u32 ch1_dfi_phy_control_0;
-	u32 ch1_dfi_phy_control_1;
-	u32 ch1_dfi_phy_control_2;
-	u32 ch1_dfi_phy_control_3;
-	u32 ch1_dfi_phy_ca_train;
-	u32 ch1_dfi_phy_ca_pattern;
-	u32 ch1_dfi_phy_write_dq_train;
-	u32 ch1_dfi_phy_leveling_status;
-	u8 reserved48[0x3e0];
-	u32 ch2_dfi_phy_control_0;
-	u32 ch2_dfi_phy_control_1;
-	u32 ch2_dfi_phy_control_2;
-	u32 ch2_dfi_phy_control_3;
-	u32 ch2_dfi_phy_ca_train;
-	u32 ch2_dfi_phy_ca_pattern;
-	u32 ch2_dfi_phy_write_dq_train;
-	u32 ch2_dfi_phy_leveling_status;
-	u8 reserved49[0x3e0];
-	u32 ch3_dfi_phy_control_0;
-	u32 ch3_dfi_phy_control_1;
-	u32 ch3_dfi_phy_control_2;
-	u32 ch3_dfi_phy_control_3;
-	u32 ch3_dfi_phy_ca_train;
-	u32 ch3_dfi_phy_ca_pattern;
-	u32 ch3_dfi_phy_write_dq_train;
-	u32 ch3_dfi_phy_leveling_status;
-};
-
-check_member(mvmap2315_mc_regs, ch3_dfi_phy_leveling_status, 0x1FFC);
-static struct mvmap2315_mc_regs * const mvmap2315_mc
-					= (void *)MVMAP2315_MC_BASE;
-
-void sdram_init(struct mvmap2315_sdram_params *sdram_params);
-size_t sdram_size_mb(void);
-
-#endif /* __SOC_MARVELL_MVMAP2315_SDRAM_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/timer.h b/src/soc/marvell/mvmap2315/include/soc/timer.h
deleted file mode 100644
index c335e4939d..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/timer.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_TIMER_H__
-#define __SOC_MARVELL_MVMAP2315_TIMER_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_CLOCKS_PER_USEC	13
-
-#define MVMAP2315_TIMER_T1CR_TE		BIT(0)
-#define MVMAP2315_TIMER_T1CR_TM		BIT(1)
-#define MVMAP2315_TIMER_T1CR_TIM	BIT(2)
-#define MVMAP2315_TIMER_T1CR_TPWM	BIT(3)
-
-struct mvmap2315_timer_regs {
-	u32 t1lc;
-	u32 t1cv;
-	u32 t1cr;
-	u32 t1eoi;
-	u32 t1is;
-	u8 _reserved0[0x8c];
-	u32 tis;
-	u32 teoi;
-	u32 tris;
-	u32 tcv;
-	u32 t1lc2;
-};
-
-check_member(mvmap2315_timer_regs, t1lc2, 0xB0);
-static struct mvmap2315_timer_regs * const mvmap2315_timer0
-					= (void *)MVMAP2315_TIMER0_BASE;
-
-#endif /* __SOC_MARVELL_MVMAP2315_TIMER_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/uart.h b/src/soc/marvell/mvmap2315/include/soc/uart.h
deleted file mode 100644
index 36b79f2e55..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/uart.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_UART_H__
-#define __SOC_MARVELL_MVMAP2315_UART_H__
-
-#include <stdint.h>
-
-extern u32 uart_num;
-
-#endif /* __SOC_MARVELL_MVMAP2315_UART_H__ */
diff --git a/src/soc/marvell/mvmap2315/include/soc/wdt.h b/src/soc/marvell/mvmap2315/include/soc/wdt.h
deleted file mode 100644
index 19715872ec..0000000000
--- a/src/soc/marvell/mvmap2315/include/soc/wdt.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Marvell, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MARVELL_MVMAP2315_WDT_H__
-#define __SOC_MARVELL_MVMAP2315_WDT_H__
-
-#include <stdint.h>
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define MVMAP2315_R4_WDT			0
-#define MVMAP2315_AP_WDT			1
-
-#define MVMAP2315_WDT_CR_RPL_SHIFT		2
-#define MVMAP2315_WDT_CR_RMOD			BIT(1)
-#define MVMAP2315_WDT_CR_EN			BIT(0)
-#define MVMAP2315_WDT_TORR_TOP_SHIFT		0
-#define MVMAP2315_WDT_CRR_SHIFT			0
-struct mvmap2315_wdt_regs {
-	u32 wdt_cr;
-	u32 wdt_torr;
-	u32 wdt_ccvr;
-	u32 wdt_crr;
-	u32 wdt_stat;
-	u32 wdt_eoi;
-	u8 _reserved0[0xcc];
-	u32 wdt_comp_params_5;
-	u32 wdt_comp_params_4;
-	u32 wdt_comp_params_3;
-	u32 wdt_comp_params_2;
-	u32 wdt_comp_params_1;
-	u32 wdt_comp_version;
-	u32 wdt_comp_type;
-};
-
-check_member(mvmap2315_wdt_regs, wdt_comp_type, 0xfc);
-
-
-void enable_sp_watchdog(u32 timer, u32 timeout_value);
-void reset_sp_watchdog(u32 timer, u32 timeout_value);
-
-#endif /* __SOC_MARVELL_MVMAP2315_WDT_H__ */