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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 09:55:57 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-30 08:05:55 +0000 |
| commit | f1b4a7c9d4e8eb5884efab2d29f49812326f66e2 (patch) | |
| tree | 13d856d5b031d7ff72b13fa59b32114b385472b4 /src/soc/intel | |
| parent | f90056268fe0280da600703baebf5a0623f019e1 (diff) | |
elog: Add new wake source codes
Tiger Lake introduces new wake-capable devices, including thunderbolt
ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE
macros for each of these types of devices.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions