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authorSubrata Banik <subrata.banik@intel.com>2021-06-21 19:26:10 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-06-23 08:26:27 +0000
commite633804375f35998bcd6f3843a0142f1c13d385e (patch)
treeb7837719f230e65e7b16873dc360e107b346d52d /src/soc/intel
parent3b374bebac10ccf08a4741e86b03d4353072d625 (diff)
soc/intel/alderlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I5e10e5d0b80986e1e73573a86a957985840fe0b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55727 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/fsp_params.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 0170eecffd..0987b41bf2 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -82,7 +82,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd;
uint32_t enable_mask;
- struct device *dev;
struct soc_intel_alderlake_config *config;
config = config_of_soc();
mainboard_update_soc_chip_config(config);
@@ -179,14 +178,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1;
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
- if (dev) {
- if (!xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
- } else {
- params->XdciEnable = 0;
- }
+ if (!xdci_can_enable())
+ devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
+ params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;