soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
	Panther Lake U/H 12Xe/H 4Xe External Design
	Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
	Volume 2 of 2 #813030

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

17 files changed, 1113 insertions, 13 deletions

diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 179d2abe12..5e5516a4f4 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -6,22 +6,31 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select ARCH_X86
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
+	select CPU_INTEL_COMMON
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select FSP_M_XIP
+	select FSP_USES_CB_DEBUG_EVENT_HANDLER
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
 	select HAVE_X86_64_SUPPORT
 	select IDT_IN_EVERY_STAGE
+	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select IOAPIC
 	select MICROCODE_BLOB_UNDISCLOSED
+	select MRC_SETTINGS_PROTECT
 	select PLATFORM_USES_FSP2_4
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_CAR
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_IOE_P2SB
+	select SOC_INTEL_COMMON_BLOCK_MEMINIT
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_IOE_DIE_SUPPORT
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER
@@ -37,10 +46,20 @@ config SOC_INTEL_PANTHERLAKE_U_H
 	bool
 	select SOC_INTEL_PANTHERLAKE_BASE
 	help
-	  Choose this option if your mainboard has a PTL-UH SoC.
+	  Choose this option if the mainboard is built using either a PTL-U (15W) or
+	  PTL-H 12Xe (25W) system-on-a-chip SoC.
 	  Note, PTL U/H processor line is offered in a single package platform that includes the
 	  Compute tile, the PCD tile, and the GFX tile on the same package.
 
+config SOC_INTEL_PANTHERLAKE_H
+	bool
+	depends on !SOC_INTEL_PANTHERLAKE_U_H
+	select SOC_INTEL_PANTHERLAKE_BASE
+	help
+	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
+	  Note, PTL-H processor line is offered in a single package platform that includes the
+	  Compute tile, the PCD tile, and the GFX tile on the same package.
+
 if SOC_INTEL_PANTHERLAKE_BASE
 
 config CAR_ENHANCED_NEM
@@ -89,6 +108,19 @@ config IED_REGION_SIZE
 	hex
 	default 0x400000
 
+config MAX_TBT_ROOT_PORTS
+	int
+	default 4
+
+config MAX_ROOT_PORTS
+	int
+	default 10 if SOC_INTEL_PANTHERLAKE_H
+	default 12
+
+config MAX_PCIE_CLOCK_SRC
+	int
+	default 9
+
 config PCR_BASE_ADDRESS
 	hex
 	default 0x4000000000
@@ -139,18 +171,6 @@ config SOC_INTEL_USB3_DEV_MAX
 	int
 	default 2
 
-config MAX_TBT_ROOT_PORTS
-	int
-	default 4
-
-config MAX_ROOT_PORTS
-	int
-	default 12
-
-config MAX_PCIE_CLOCK_SRC
-	int
-	default 9
-
 config CONSOLE_UART_BASE_ADDRESS
 	hex
 	default 0xfe02c000
@@ -194,4 +214,54 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 	default 0x100000 if BUILDING_WITH_DEBUG_FSP
 	default 0x40000
 
+config FSP_HEADER_PATH
+	string "Location of FSP headers"
+	default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/"
+
+config SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT
+	int "Debug Consent"
+	# USB DBC is more common for developers so make this default to 4 if
+	# SOC_INTEL_DEBUG_CONSENT=y
+	default 4 if SOC_INTEL_DEBUG_CONSENT
+	default 0
+	help
+	  This is to control debug interface on SOC.
+	  Setting non-zero value will allow to use DBC or DCI to debug SOC.
+	  PlatformDebugConsent in FspmUpd.h has the details.
+
+	  Desired platform debug type are
+	  0:Disabled,
+	  2:Enabled Trace active: TraceHub is enabled and trace is active,
+	  blocks s0ix,
+	  4:Enabled Trace ready: TraceHub is enabled and allowed S0ix,
+	  6:Enabled Trace power off: TraceHub is powergated, provide setting close to
+	  functional low power state,
+	  7:user needs to configure Advanced Debug Settings manually.
+
+config DATA_BUS_WIDTH
+	int
+	default 128
+
+config DIMMS_PER_CHANNEL
+	int
+	default 2
+
+config MRC_CHANNEL_WIDTH
+	int
+	default 16
+
+config BUILDING_WITH_DEBUG_FSP
+	bool "Debug FSP is used for the build"
+	default n
+	help
+	  Set this option if debug build of FSP is used.
+
+config FSP_PUBLISH_MBP_HOB
+	bool
+	default n if CHROMEOS
+	default y
+	help
+	  This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
+	  Disabling it for the platforms, which do not use MBP HOB, can improve the boot time.
+
 endif
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 106934a810..477a5d7706 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -2,6 +2,7 @@
 
 ifeq ($(CONFIG_SOC_INTEL_PANTHERLAKE_BASE),y)
 
+subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
@@ -11,6 +12,12 @@ bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
 bootblock-y += soc_info.c
 
+romstage-y += espi.c
+romstage-y += meminit.c
+romstage-y += pcie_rp.c
+romstage-y += reset.c
+romstage-y += soc_info.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake/include
 
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
new file mode 100644
index 0000000000..589ce14eed
--- /dev/null
+++ b/src/soc/intel/pantherlake/chip.h
@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_CHIP_H_
+#define _SOC_PANTHERLAKE_CHIP_H_
+
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/power_limit.h>
+#include <intelblocks/pcie_rp.h>
+#include <intelblocks/tcss.h>
+#include <soc/gpe.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/serialio.h>
+#include <soc/usb.h>
+#include <stdint.h>
+
+/* Define config parameters for In-Band ECC (IBECC). */
+#define MAX_IBECC_REGIONS 8
+
+/* In-Band ECC Operation Mode */
+enum ibecc_mode {
+	IBECC_MODE_PER_REGION,
+	IBECC_MODE_NONE,
+	IBECC_MODE_ALL
+};
+
+struct ibecc_config {
+	bool enable;
+	bool parity_en;
+	enum ibecc_mode mode;
+	bool region_enable[MAX_IBECC_REGIONS];
+	uint16_t region_base[MAX_IBECC_REGIONS];
+	uint16_t region_mask[MAX_IBECC_REGIONS];
+};
+
+/* Types of different SKUs */
+enum soc_intel_pantherlake_power_limits {
+	PTL_U_15W_POWER_LIMITS,
+	PTL_H_25W_POWER_LIMITS,
+	PTL_H_45W_POWER_LIMITS,
+	PTL_POWER_LIMITS_COUNT,
+};
+
+/* Types of display ports */
+enum ddi_ports {
+	DDI_PORT_A,
+	DDI_PORT_B,
+	DDI_PORT_C,
+	DDI_PORT_1,
+	DDI_PORT_2,
+	DDI_PORT_3,
+	DDI_PORT_4,
+	DDI_PORT_COUNT,
+};
+
+enum ddi_port_flags {
+	DDI_ENABLE_DDC = BIT(0), /* Display Data Channel */
+	DDI_ENABLE_HPD = BIT(1), /* Hot Plug Detect */
+};
+
+struct soc_intel_pantherlake_config {
+
+	/* Common struct containing soc config data required by common code */
+	struct soc_intel_common_config common_soc_config;
+
+	/* Common struct containing power limits configuration information */
+	struct soc_power_limits_config power_limits_config[PTL_POWER_LIMITS_COUNT];
+
+	/* Gpio group routed to each dword of the GPE0 block. Values are
+	 * of the form PMC_GPP_[A:U] or GPD. */
+	uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
+	uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
+	uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
+
+	/* Generic IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
+
+	/* Enable S0iX support */
+	int s0ix_enable;
+	/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
+	uint8_t tcss_d3_hot_disable;
+	/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
+	uint8_t TcssD3ColdDisable;
+	/* Enable DPTF support */
+	int dptf_enable;
+
+	/* Deep SX enable for both AC and DC */
+	int deep_s3_enable_ac;
+	int deep_s3_enable_dc;
+	int deep_s5_enable_ac;
+	int deep_s5_enable_dc;
+
+	/* Deep Sx Configuration
+	 *  DSX_EN_WAKE_PIN       - Enable WAKE# pin
+	 *  DSX_EN_LAN_WAKE_PIN   - Enable LAN_WAKE# pin
+	 *  DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
+	uint32_t deep_sx_config;
+
+	/* TCC activation offset */
+	uint32_t tcc_offset;
+
+	/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
+	 * When enabled memory will be training at two different frequencies.
+	 * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
+	 * 4:FixedPoint3, 5:Enabled */
+	enum {
+		SaGv_Disabled,
+		SaGv_FixedPoint0,
+		SaGv_FixedPoint1,
+		SaGv_FixedPoint2,
+		SaGv_FixedPoint3,
+		SaGv_Enabled,
+	} sagv;
+
+	/* Rank Margin Tool. 1:Enable, 0:Disable */
+	uint8_t rmt;
+
+	/* USB related */
+	struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX];
+	struct usb3_port_config usb3_ports[CONFIG_SOC_INTEL_USB3_DEV_MAX];
+	uint8_t usb2_port_reset_msg_en[CONFIG_SOC_INTEL_USB2_DEV_MAX];
+	/* Wake Enable Bitmap for USB2 ports */
+	uint16_t usb2_wake_enable_bitmap;
+	/* Wake Enable Bitmap for USB3 ports */
+	uint16_t usb3_wake_enable_bitmap;
+	/* Program OC pins for TCSS */
+	struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
+	uint8_t tbt_pcie_port_disable[4];
+	uint8_t tcss_cap_policy[4];
+	/* Validate TBT firmware authenticated and loaded into IMR */
+	bool tbt_authentication;
+
+	/* Audio related */
+	uint8_t pch_hda_dsp_enable;
+
+	/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
+	enum {
+		HDA_TMODE_2T = 0,
+		HDA_TMODE_4T = 2,
+		HDA_TMODE_8T = 3,
+		HDA_TMODE_16T = 4,
+	} pch_hda_idisp_link_tmode;
+
+	/* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
+	enum {
+		HDA_LINKFREQ_48MHZ = 3,
+		HDA_LINKFREQ_96MHZ = 4,
+	} pch_hda_idisp_link_frequency;
+
+	bool pch_hda_idisp_codec_enable;
+
+	struct pcie_rp_config pcie_rp[CONFIG_MAX_ROOT_PORTS];
+	uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
+
+	/* Gfx related */
+	enum {
+		IGD_SM_0MB = 0x00,
+		IGD_SM_32MB = 0x01,
+		IGD_SM_64MB = 0x02,
+		IGD_SM_128MB = 0x03,
+		IGD_SM_4MB = 0xF0,
+		IGD_SM_8MB = 0xF1,
+		IGD_SM_12MB = 0xF2,
+		IGD_SM_16MB = 0xF3,
+		IGD_SM_20MB = 0xF4,
+		IGD_SM_24MB = 0xF5,
+		IGD_SM_28MB = 0xF6,
+		IGD_SM_36MB = 0xF8,
+		IGD_SM_40MB = 0xF9,
+		IGD_SM_44MB = 0xFA,
+		IGD_SM_48MB = 0xFB,
+		IGD_SM_52MB = 0xFC,
+		IGD_SM_56MB = 0xFD,
+		IGD_SM_60MB = 0xFE,
+	} IgdDvmt50PreAlloc;
+	uint8_t skip_ext_gfx_scan;
+
+	/* CNVi WiFi Core Enable/Disable */
+	bool cnvi_wifi_core;
+
+	/* CNVi BT Core Enable/Disable */
+	bool cnvi_bt_core;
+
+	/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
+	bool cnvi_bt_audio_offload;
+
+	/* In-Band ECC (IBECC) configuration */
+	struct ibecc_config ibecc;
+
+	/* HeciEnabled decides the state of Heci1 at end of boot
+	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
+	uint8_t HeciEnabled;
+
+	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	uint8_t eist_enable;
+
+	/* Enable C6 DRAM */
+	uint8_t enable_c6dram;
+	uint8_t PmTimerDisabled;
+	/*
+	 * SerialIO device mode selection:
+	 * PchSerialIoDisabled,
+	 * PchSerialIoPci,
+	 * PchSerialIoHidden,
+	 * PchSerialIoLegacyUart,
+	 * PchSerialIoSkipInit
+	 */
+	uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+	uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+	uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
+	/*
+	 * GSPIn Default Chip Select Mode:
+	 * 0:Hardware Mode,
+	 * 1:Software Mode
+	 */
+	uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+	/*
+	 * GSPIn Default Chip Select State:
+	 * 0: Low,
+	 * 1: High
+	 */
+	uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
+	/* Debug interface selection */
+	enum {
+		DEBUG_INTERFACE_RAM = BIT(0),
+		DEBUG_INTERFACE_UART_8250IO = BIT(1),
+		DEBUG_INTERFACE_USB3 = BIT(3),
+		DEBUG_INTERFACE_LPSS_SERIAL_IO = BIT(4),
+		DEBUG_INTERFACE_TRACEHUB = BIT(5),
+	} debug_interface_flag;
+
+	/*
+	 * These GPIOs will be programmed by the IOM to handle biasing of the
+	 * Type-C aux (SBU) signals when certain alternate modes are used.
+	 * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
+	 * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
+	 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
+	 * (name often contains `AUXP_DC` or `_AUX_P`).
+	 */
+	struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
+
+	/*
+	 * SOC Aux orientation override:
+	 * This is a bitfield that corresponds to up to 4 TCSS ports on PTL.
+	 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
+	 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
+	 * on the motherboard.
+	 */
+	uint16_t tcss_aux_ori;
+
+	/* Connect Topology Command timeout value */
+	uint16_t itbt_connect_topology_timeout_in_ms;
+
+	/*
+	 * Override GPIO PM configuration:
+	 * 0: Use FSP default GPIO PM program,
+	 * 1: coreboot to override GPIO PM program
+	 */
+	uint8_t gpio_override_pm;
+
+	/*
+	 * GPIO PM configuration: 0 to disable, 1 to enable power gating
+	 * Bit 6-7: Reserved
+	 * Bit 5: MISCCFG_GPSIDEDPCGEN
+	 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
+	 * Bit 3: MISCCFG_GPRTCDLCGEN
+	 * Bit 2: MISCCFG_GSXLCGEN
+	 * Bit 1: MISCCFG_GPDPCGEN
+	 * Bit 0: MISCCFG_GPDLCGEN
+	 */
+	uint8_t gpio_pm[TOTAL_GPIO_COMM];
+
+	/* DP config */
+	/*
+	 * Port config
+	 * 0:Disabled, 1:eDP, 2:MIPI DSI
+	 */
+	uint8_t ddi_port_A_config;
+	uint8_t ddi_port_B_config;
+
+	/* Enable(1)/Disable(0) HPD/DDC */
+	uint8_t ddi_ports_config[DDI_PORT_COUNT];
+
+	/* Hybrid storage mode enable (1) / disable (0)
+	 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
+	 * accordingly */
+	uint8_t HybridStorageMode;
+
+	/*
+	 * Override CPU flex ratio value:
+	 * CPU ratio value controls the maximum processor non-turbo ratio.
+	 * Valid Range 0 to 63.
+	 *
+	 * In general descriptor provides option to set default cpu flex ratio.
+	 * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
+	 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+	 *
+	 * Only override CPU flex ratio if don't want to boot with non-turbo max.
+	 */
+	uint8_t cpu_ratio_override;
+
+	/*
+	 * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
+	 * Default 0. Setting this to 1 disables the DMI Power Optimizer.
+	 */
+	uint8_t DmiPwrOptimizeDisable;
+
+	/*
+	 * Enable(1)/Disable(0) CPU Replacement check.
+	 * Default 0. Setting this to 1 to check CPU replacement.
+	 */
+	uint8_t cpu_replacement_check;
+
+	/* ISA Serial Base selection. */
+	enum {
+		ISA_SERIAL_BASE_ADDR_3F8,
+		ISA_SERIAL_BASE_ADDR_2F8,
+	} IsaSerialUartBase;
+
+	/* USB overcurrent pin mapping */
+	uint8_t pch_usb_oc_enable;
+};
+
+typedef struct soc_intel_pantherlake_config config_t;
+
+#endif /* _SOC_PANTHERLAKE_CHIP_H_ */
diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb
new file mode 100644
index 0000000000..91e21c09f7
--- /dev/null
+++ b/src/soc/intel/pantherlake/chipset.cb
@@ -0,0 +1,158 @@
+chip soc/intel/pantherlake
+
+	device cpu_cluster 0 on end
+
+	register "power_limits_config[PTL_U_15W_POWER_LIMITS]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 54,
+		.tdp_pl4 = 142,
+	}"
+
+	# NOTE: if any variant wants to override this value, use the same format
+	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
+	# putting it under register "common_soc_config" in overridetree.cb file.
+	register "common_soc_config.pch_thermal_trip" = "125"
+
+	device domain 0 on
+		device pci 00.0 alias system_agent on end
+		device pci 02.0 alias igpu on end
+		device pci 04.0 alias dtt off end
+		device pci 05.0 alias ipu off end
+		device pci 06.0 alias pcie_rp9 off end
+		device pci 06.1 alias pcie_rp10 off end
+		device pci 06.2 alias pcie_rp11 off end
+		device pci 06.3 alias pcie_rp12 off end
+		device pci 07.0 alias tbt_pcie_rp0 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma0 as usb4_port
+				device generic 0 on end
+			end
+		end
+		device pci 07.1 alias tbt_pcie_rp1 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma0 as usb4_port
+				device generic 1 on end
+			end
+		end
+		device pci 07.2 alias tbt_pcie_rp2 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma1 as usb4_port
+				device generic 0 on end
+			end
+		end
+		device pci 07.3 alias tbt_pcie_rp3 off
+			chip soc/intel/common/block/usb4
+				use tcss_dma1 as usb4_port
+				device generic 1 on end
+			end
+		end
+		device pci 0a.0 alias crashlog on end
+		device pci 0b.0 alias npu off end
+		device pci 0c.0 alias iaa on end
+		device pci 0d.0 alias tcss_xhci off
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias tcss_root_hub off
+					chip drivers/usb/acpi
+						device usb 3.0 alias tcss_usb3_port0 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias tcss_usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.2 alias tcss_usb3_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 alias tcss_usb3_port3 off end
+					end
+				end
+			end
+		end
+		device pci 0d.1 alias tcss_xdci off end
+		device pci 0d.2 alias tcss_dma0 off end
+		device pci 0d.3 alias tcss_dma1 off end
+		device pci 10.0 alias thc0 off end
+		device pci 10.1 alias thc1 off end
+		device pci 12.0 alias ish off end
+		device pci 12.1 alias p2sb2 hidden end
+		device pci 12.6 alias gspi2 off end
+		device pci 13.0 alias heci_1 off end
+		device pci 13.1 alias heci_2 off end
+		device pci 13.2 alias heci_3 off end
+		device pci 14.0 alias xhci on
+			chip drivers/usb/acpi
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 alias xhci_root_hub off
+					chip drivers/usb/acpi
+						device usb 2.0 alias usb2_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.1 alias usb2_port2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.2 alias usb2_port3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 alias usb2_port4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 alias usb2_port5 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 alias usb2_port6 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.6 alias usb2_port7 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.7 alias usb2_port8 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.0 alias usb3_port1 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.1 alias usb3_port2 off end
+					end
+				end
+			end
+		end
+		device pci 14.2 alias shared_sram off end
+		device pci 14.3 alias cnvi_wifi off end
+		device pci 14.7 alias cnvi_bluetooth off end
+		device pci 14.5 alias ieh off end
+		device pci 15.0 alias i2c0 off end
+		device pci 15.1 alias i2c1 off end
+		device pci 15.2 alias i2c2 off end
+		device pci 15.3 alias i2c3 off end
+		device pci 16.0 alias heci1 on end
+		device pci 16.1 alias heci2 off end
+		device pci 16.4 alias heci3 off end
+		device pci 16.5 alias heci4 off end
+		device pci 18.0 alias eheci1 off end
+		device pci 18.1 alias eheci2 off end
+		device pci 18.2 alias eheci3 off end
+		device pci 19.0 alias i2c4 off end
+		device pci 19.1 alias i2c5 off end
+		device pci 19.2 alias uart2 off end
+		device pci 1c.0 alias pcie_rp1 off end
+		device pci 1c.1 alias pcie_rp2 off end
+		device pci 1c.2 alias pcie_rp3 off end
+		device pci 1c.3 alias pcie_rp4 off end
+		device pci 1c.4 alias pcie_rp5 off end
+		device pci 1c.5 alias pcie_rp6 off end
+		device pci 1c.6 alias pcie_rp7 off end
+		device pci 1c.7 alias pcie_rp8 off end
+		device pci 1e.0 alias uart0 off end
+		device pci 1e.1 alias uart1 off end
+		device pci 1e.2 alias gspi0 off end
+		device pci 1e.3 alias gspi1 off end
+		device pci 1f.0 alias soc_espi on end
+		device pci 1f.1 alias p2sb hidden end
+		device pci 1f.2 alias pmc hidden end
+		device pci 1f.3 alias hda off end
+		device pci 1f.4 alias smbus off end
+		device pci 1f.5 alias fast_spi on end
+		device pci 1f.6 alias gbe off end
+		device pci 1f.7 alias npk off end
+	end
+end
diff --git a/src/soc/intel/pantherlake/include/soc/gpe.h b/src/soc/intel/pantherlake/include/soc/gpe.h
new file mode 100644
index 0000000000..eb9a8bff85
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/gpe.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_GPE_H_
+#define _SOC_PANTHERLAKE_GPE_H_
+
+#include <intelpch/gpe.h>
+
+#endif /* _SOC_PANTHERLAKE_GPE_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h
new file mode 100644
index 0000000000..78c509b519
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/meminit.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_MEMINIT_H_
+#define _SOC_PANTHERLAKE_MEMINIT_H_
+
+#include <fsp/soc_binding.h>
+#include <intelblocks/meminit.h>
+#include <types.h>
+
+enum mem_type {
+	MEM_TYPE_LP5X,
+};
+
+struct lpx_dq {
+	uint8_t dq0[BITS_PER_BYTE];
+	uint8_t dq1[BITS_PER_BYTE];
+};
+
+struct lpx_dqs {
+	uint8_t dqs0;
+	uint8_t dqs1;
+};
+
+struct lpx_dq_map {
+	struct lpx_dq ddr0;
+	struct lpx_dq ddr1;
+	struct lpx_dq ddr2;
+	struct lpx_dq ddr3;
+	struct lpx_dq ddr4;
+	struct lpx_dq ddr5;
+	struct lpx_dq ddr6;
+	struct lpx_dq ddr7;
+};
+
+struct lpx_dqs_map {
+	struct lpx_dqs ddr0;
+	struct lpx_dqs ddr1;
+	struct lpx_dqs ddr2;
+	struct lpx_dqs ddr3;
+	struct lpx_dqs ddr4;
+	struct lpx_dqs ddr5;
+	struct lpx_dqs ddr6;
+	struct lpx_dqs ddr7;
+};
+
+struct mem_lp5x_config {
+	uint8_t ccc_config;
+};
+
+struct rcomp {
+	/*
+	 * Rcomp resistor value. This values represents the resistance in
+	 * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC.
+	 *
+	 * Note: If mainboard users don't want to override rcomp related settings
+	 * then associated rcomp UPDs will have its default value.
+	 */
+	uint16_t resistor;
+	/* Rcomp target values. */
+	uint16_t targets[5];
+};
+
+struct mb_cfg {
+	enum mem_type type;
+	struct rcomp rcomp;
+	union {
+		/*
+		 * DQ CPU<>DRAM map:
+		 * Index of the array represents DQ# on the CPU and the value represents DQ# on
+		 * the DRAM part.
+		 */
+		uint8_t dq_map[CONFIG_DATA_BUS_WIDTH];
+		struct lpx_dq_map lpx_dq_map;
+	};
+
+	union {
+		/*
+		 * DQS CPU<>DRAM map:
+		 * Index of the array represents DQS# on the CPU and the value represents DQS#
+		 * on the DRAM part.
+		 */
+		uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE];
+		struct lpx_dqs_map lpx_dqs_map;
+	};
+
+	struct mem_lp5x_config lp5x_config;
+
+	/* Early Command Training Enable/Disable Control */
+	bool ect;
+
+	/* Board type */
+	uint8_t user_bd;
+
+	/* Command Mirror */
+	uint8_t cmd_mirror;
+
+	/* Enable/Disable TxDqDqs Retraining for LP5 */
+	uint8_t lp_ddr_dq_dqs_re_training;
+};
+
+void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
+		 const struct mem_spd *spd_info, bool half_populated);
+
+#endif /* _SOC_PANTHERLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/msr.h b/src/soc/intel/pantherlake/include/soc/msr.h
new file mode 100644
index 0000000000..a268cd2af6
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/msr.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_MSR_H_
+#define _SOC_PANTHERLAKE_MSR_H_
+
+#include <intelblocks/msr.h>
+
+#define MSR_BIOS_DONE		        0x151
+#define   ENABLE_IA_UNTRUSTED	        BIT(0)
+
+#endif /* _SOC_PANTHERLAKE_MSR_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/pmc.h b/src/soc/intel/pantherlake/include/soc/pmc.h
new file mode 100644
index 0000000000..daa60f2080
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/pmc.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_PMC_H_
+#define _SOC_PANTHERLAKE_PMC_H_
+#include <device/device.h>
+
+extern struct device_operations pmc_ops;
+
+/* PCI Configuration Space (D31:F2): PMC */
+#define  PWRMBASE		0x10
+#define  ABASE			0x20
+
+/* General PM Configuration A */
+#define GEN_PMCON_A			0x1020
+#define   DC_PP_DIS			BIT(30)
+#define   DSX_PP_DIS			BIT(29)
+#define   AG3_PP_EN			BIT(28)
+#define   SX_PP_EN			BIT(27)
+#define   ALLOW_ICLK_PLL_SD_INC0	BIT(26)
+#define   GBL_RST_STS			BIT(24)
+#define   DISB				BIT(23)
+#define   ALLOW_OPI_PLL_SD_INC0		BIT(22)
+#define   MEM_SR			BIT(21)
+#define   ALLOW_SPXB_CG_INC0		BIT(20)
+#define   ALLOW_L1LOW_C0		BIT(19)
+#define   MS4V				BIT(18)
+#define   ALLOW_L1LOW_OPI_ON		BIT(17)
+#define   SUS_PWR_FLR			BIT(16)
+#define   PME_B0_S5_DIS			BIT(15)
+#define   PWR_FLR			BIT(14)
+#define   ALLOW_L1LOW_BCLKREQ_ON	BIT(13)
+#define   DIS_SLP_X_STRCH_SUS_UP	BIT(12)
+#define   SLP_S3_MIN_ASST_WDTH_MASK	(3 << 10)
+#define     SLP_S3_MIN_ASST_WDTH_60USEC	(0 << 10)
+#define     SLP_S3_MIN_ASST_WDTH_1MS	BIT(10)
+#define     SLP_S3_MIN_ASST_WDTH_50MS	(2 << 10)
+#define     SLP_S3_MIN_ASST_WDTH_2S	(3 << 10)
+#define   HOST_RST_STS			BIT(9)
+#define   ESPI_SMI_LOCK			BIT(8)
+#define   S4MAW_MASK			(3 << 4)
+#define     S4MAW_1S			BIT(4)
+#define     S4MAW_2S			(2 << 4)
+#define     S4MAW_3S			(3 << 4)
+#define     S4MAW_4S			(0 << 4)
+#define     S4ASE			BIT(3)
+#define   PER_SMI_SEL_MASK		(3 << 1)
+#define     SMI_RATE_64S		(0 << 1)
+#define     SMI_RATE_32S		BIT(1)
+#define     SMI_RATE_16S		(2 << 1)
+#define     SMI_RATE_8S			(3 << 1)
+#define   SLEEP_AFTER_POWER_FAIL	BIT(0)
+
+/* General PM Configuration B */
+#define GEN_PMCON_B			0x1024
+#define   ST_FDIS_LOCK			BIT(21)
+#define   SLP_STR_POL_LOCK		BIT(18)
+#define   ACPI_BASE_LOCK		BIT(17)
+#define   PM_DATA_BAR_DIS		BIT(16)
+#define   WOL_EN_OVRD			BIT(13)
+#define   BIOS_PCI_EXP_EN		BIT(10)
+#define   PWRBTN_LVL			BIT(9)
+#define   SMI_LOCK			BIT(4)
+#define   RTC_BATTERY_DEAD		BIT(2)
+
+/* Extended Test Mode Register */
+#define ETR				0x1048
+#define   CF9_LOCK			BIT(31)
+#define   CF9_GLB_RST			BIT(20)
+
+/* Set strap message lock */
+#define SSML				0x104C
+#define   SSML_SSL_DS			(0 << 0)
+#define   SSML_SSL_EN			BIT(0)
+
+/* Set strap msg control */
+#define SSMC				0x1050
+#define   SSMC_SSMS			BIT(0)
+
+/* Set strap message data */
+#define SSMD				0x1054
+#define   SSMD_SSD_MASK			(0xffff << 0)
+
+/* Power and Reset Status */
+#define PRSTS				0x1810
+
+/* Power Management Configuration */
+#define PM_CFG				0x1818
+#define   PM_CFG_DBG_MODE_LOCK		BIT(27)
+#define   PM_CFG_XRAM_READ_DISABLE	BIT(22)
+
+/* S3 Power Gating Policies */
+#define S3_PWRGATE_POL			0x1828
+#define   S3DC_GATE_SUS			BIT(1)
+#define   S3AC_GATE_SUS			BIT(0)
+
+/* S4 power gating policies */
+#define S4_PWRGATE_POL			0x182c
+#define   S4DC_GATE_SUS			BIT(1)
+#define   S4AC_GATE_SUS			BIT(0)
+
+/* S5 power gating policies */
+#define S5_PWRGATE_POL			0x1830
+#define   S5DC_GATE_SUS			BIT(15)
+#define   S5AC_GATE_SUS			BIT(14)
+
+/* Deep Sx configuration */
+#define DSX_CFG				0x1834
+#define   REQ_CNV_NOWAKE_DSX		BIT(4)
+#define   REQ_BATLOW_DSX		BIT(3)
+#define   DSX_EN_WAKE_PIN		BIT(2)
+#define   DSX_DIS_AC_PRESENT_PD	BIT(1)
+#define   DSX_EN_LAN_WAKE_PIN		BIT(0)
+#define DSX_CFG_MASK			(0x1f << 0)
+
+#define PMSYNC_TPR_CFG			0x18C4
+#define   PCH2CPU_TPR_CFG_LOCK		BIT(31)
+#define   PCH2CPU_TT_EN			BIT(26)
+
+/* ACPI Timer Control */
+#define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define   ACPI_TIM_DIS			BIT(1)
+#define GPIO_GPE_CFG			0x1920
+#define   GPE0_DWX_MASK			0xf
+#define   GPE0_DW_SHIFT(x)		(4*(x))
+
+/* GPIO community groups */
+#define PMC_GPP_V		0x0
+#define PMC_GPP_C		0x1
+#define PMC_GPP_F		0x2
+#define PMC_GPP_E		0x3
+#define PMC_GPP_A		0x4
+#define PMC_GPP_H		0x5
+#define PMC_GPP_VGPIO		0x6
+#define PMC_GPP_B		0x7
+#define PMC_GPP_D		0x8
+#define PMC_GPP_S		0x9
+
+/* Global reset causes 0 */
+#define GBLRST_CAUSE0			0x1924
+#define   GBLRST_CAUSE0_THERMTRIP	BIT(5)
+
+/* Global reset causes 1 */
+#define GBLRST_CAUSE1			0x1928
+
+/* Host partition reset causes */
+#define HPR_CAUSE0			0x192C
+#define   HPR_CAUSE0_MI_HRPD		BIT(10)
+#define   HPR_CAUSE0_MI_HRPC		BIT(9)
+#define   HPR_CAUSE0_MI_HR		BIT(8)
+
+/* Sleep S0 residency */
+#define SLP_S0_RES			0x193c
+
+#define CPPMVRIC			0x1B1C
+#define   XTALSDQDIS			BIT(22)
+
+#define IRQ_REG				ACTL
+#define SCI_IRQ_ADJUST			0
+
+/* ACPI Control */
+#define ACTL				0x1BD8
+#define   PWRM_EN			BIT(8)
+#define   ACPI_EN			BIT(7)
+#define   SCI_IRQ_SEL			(7 << 0)
+
+#define  SCIS_IRQ9			0
+#define  SCIS_IRQ10			1
+#define  SCIS_IRQ11			2
+#define  SCIS_IRQ20			4
+#define  SCIS_IRQ21			5
+#define  SCIS_IRQ22			6
+#define  SCIS_IRQ23			7
+
+#endif /* _SOC_PANTHERLAKE_PMC_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/romstage.h b/src/soc/intel/pantherlake/include/soc/romstage.h
new file mode 100644
index 0000000000..733a11b7aa
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/romstage.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_ROMSTAGE_H_
+#define _SOC_PANTHERLAKE_ROMSTAGE_H_
+
+#include <fsp/api.h>
+#include <soc/soc_chip.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd);
+void systemagent_early_init(void);
+
+/* Board type */
+enum board_type {
+	BOARD_TYPE_MOBILE  = 0,
+	BOARD_TYPE_DESKTOP = 1,
+	BOARD_TYPE_ULT_ULX = 5,
+	BOARD_TYPE_SERVER  = 7
+};
+
+#endif /* _SOC_PANTHERLAKE_ROMSTAGE_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/soc_chip.h b/src/soc/intel/pantherlake/include/soc/soc_chip.h
new file mode 100644
index 0000000000..a1d064b5bb
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/soc_chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_SOC_CHIP_H_
+#define _SOC_PANTHERLAKE_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_PANTHERLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/systemagent.h b/src/soc/intel/pantherlake/include/soc/systemagent.h
new file mode 100644
index 0000000000..c791e5bbe8
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/systemagent.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_SYSTEMAGENT_H_
+#define _SOC_PANTHERLAKE_SYSTEMAGENT_H_
+
+#include <intelblocks/systemagent.h>
+
+/* Device 0:0.0 PCI configuration space */
+
+#define SAFBAR		0x68
+#define EPBAR		0x40
+#define CAPID0_A	0xe4
+#define  VTD_DISABLE	(1 << 23)
+
+/* MCHBAR offsets */
+#define VTDBAR			0x5410
+#define GFXVTBAR		VTDBAR
+#define REGBAR			0x5420
+#define MCH_DDR_POWER_LIMIT_LO	0x58e0
+#define MCH_DDR_POWER_LIMIT_HI	0x58e4
+#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define BIOS_RESET_CPL		0x5da8
+#define IMRBASE			0x6a40
+#define IMRLIMIT		0x6a48
+#define IPUVTBAR		0x7880
+#define TBTxBAR(x)		(0x7888 + (x) * 8)
+
+#define MAX_TBT_PCIE_PORT	4
+
+#define VTBAR_ENABLED		0x01
+#define VTBAR_MASK		0x7ffffff000ull
+
+static const struct sa_mmio_descriptor soc_vtd_resources[] = {
+	{ VTDBAR, VTD_BASE_ADDRESS, VTD_BASE_SIZE, "VTDBAR" },
+};
+
+#define V_P2SB_CFG_IBDF_BUS	0
+#define V_P2SB_CFG_IBDF_DEV	30
+#define V_P2SB_CFG_IBDF_FUNC	7
+#define V_P2SB_CFG_HBDF_BUS	0
+#define V_P2SB_CFG_HBDF_DEV	30
+#define V_P2SB_CFG_HBDF_FUNC	6
+
+#define CRAB_ABORT_BASE_ADDR	0xFEB00000
+#define CRAB_ABORT_SIZE		(512 * KiB)
+#define TPM_BASE_ADDRESS	0xFED40000
+#define TPM_SIZE		(64 * KiB)
+#define LT_SECURITY_BASE_ADDR	0xFED20000
+#define LT_SECURITY_SIZE	(384 * KiB)
+#define APIC_SIZE		(1 * MiB)
+
+#define MASK_PCIEXBAR_LENGTH	0x0000000E // bits [3:1]
+#define PCIEXBAR_LENGTH_LSB	1 // used to shift right
+
+#define  DSM_BASE_ADDR_REG	0xB0
+#define  MASK_DSM_LENGTH	0xFF00 // [15:8]
+#define  MASK_DSM_LENGTH_LSB	8 // used to shift right
+#define  MASK_GSM_LENGTH	0xC0 // [7:6]
+#define  MASK_GSM_LENGTH_LSB	6 // used to shift right
+#define  DPR_REG		0x5C
+#define  MASK_DPR_LENGTH	0xFF0 // [11:4]
+#define  MASK_DPR_LENGTH_LSB	4 // used to shift right
+
+uint64_t get_mmcfg_size(const struct device *dev);
+uint64_t get_dsm_size(const struct device *dev);
+uint64_t get_gsm_size(const struct device *dev);
+uint64_t get_dpr_size(const struct device *dev);
+
+#endif /* _SOC_PANTHERLAKE_SYSTEMAGENT_H_ */
diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c
new file mode 100644
index 0000000000..40dbf378c0
--- /dev/null
+++ b/src/soc/intel/pantherlake/meminit.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <fsp/util.h>
+#include <soc/meminit.h>
+#include <string.h>
+
+void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
+		 const struct mem_spd *spd_info, bool half_populated)
+{
+	/* Update after FSP is released externally released. */
+}
diff --git a/src/soc/intel/pantherlake/reset.c b/src/soc/intel/pantherlake/reset.c
new file mode 100644
index 0000000000..bc5815ac7a
--- /dev/null
+++ b/src/soc/intel/pantherlake/reset.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cf9_reset.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <soc/intel/common/reset.h>
+
+void do_global_reset(void)
+{
+	/* Ask CSE to do the global reset */
+	if (cse_request_global_reset())
+		return;
+
+	/* global reset if CSE fail to reset */
+	pmc_global_reset_enable(1);
+	do_full_reset();
+}
diff --git a/src/soc/intel/pantherlake/romstage/Makefile.mk b/src/soc/intel/pantherlake/romstage/Makefile.mk
new file mode 100644
index 0000000000..99c1d2ca25
--- /dev/null
+++ b/src/soc/intel/pantherlake/romstage/Makefile.mk
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += fsp_params.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
+romstage-y += romstage.c
+romstage-y += systemagent.c
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
new file mode 100644
index 0000000000..6b1aa36777
--- /dev/null
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+	 /* TODO: Placeholder for overriding FSP-M UPDs */
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/pantherlake/romstage/romstage.c b/src/soc/intel/pantherlake/romstage/romstage.c
new file mode 100644
index 0000000000..a05adc455e
--- /dev/null
+++ b/src/soc/intel/pantherlake/romstage/romstage.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/smbus.h>
+#include <intelblocks/thermal.h>
+#include <memory_info.h>
+#include <soc/intel/common/smbios.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+#include <timestamp.h>
+
+/* Save the DIMM information for SMBIOS table 17 */
+static void save_dimm_info(void)
+{
+	/* Update after FSP is released externally released. */
+}
+
+void mainboard_romstage_entry(void)
+{
+	struct chipset_power_state *ps = pmc_get_power_state();
+	bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
+
+	/* Initialize HECI interface */
+	cse_init(HECI1_BASE_ADDRESS);
+
+	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
+		cse_fill_bp_info();
+		if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE))
+			cse_fw_sync();
+	}
+
+	/* Update coreboot timestamp table with CSE timestamps */
+	if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
+		cse_get_telemetry_data();
+
+	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+	systemagent_early_init();
+	/* Program SMBus base address and enable it */
+	smbus_common_init();
+
+	/*
+	 * Set low maximum temp threshold value used for dynamic thermal sensor
+	 * shutdown consideration.
+	 *
+	 * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+	 * thermal sensor when CPU is in a C-state and LTT >= DTS Temp.
+	 */
+	pch_thermal_configuration();
+	fsp_memory_init(s3wake);
+	pmc_set_disb();
+	if (!s3wake)
+		save_dimm_info();
+}
diff --git a/src/soc/intel/pantherlake/romstage/systemagent.c b/src/soc/intel/pantherlake/romstage/systemagent.c
new file mode 100644
index 0000000000..951f92083e
--- /dev/null
+++ b/src/soc/intel/pantherlake/romstage/systemagent.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
+
+void systemagent_early_init(void)
+{
+	static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+		{ SAFBAR, SAF_BASE_ADDRESS, SAF_BASE_SIZE, "SAFBAR" },
+		{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+	};
+
+	static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
+		{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
+	};
+
+	/* Set Fixed MMIO address into PCI configuration space */
+	sa_set_pci_bar(soc_fixed_pci_resources,
+		       ARRAY_SIZE(soc_fixed_pci_resources));
+	/* Set Fixed MMIO address into MCH base address */
+	sa_set_mch_bar(soc_fixed_mch_resources,
+		       ARRAY_SIZE(soc_fixed_mch_resources));
+	/* Enable PAM registers */
+	enable_pam_region();
+}