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authorSean Rhodes <sean@starlabs.systems>2022-09-15 12:16:30 +0100
committerAngel Pons <th3fanbus@gmail.com>2022-10-15 22:33:54 +0000
commitd9ef02ce1d26767c3ddc36499223a91d77962bbb (patch)
treef6e09cc809a83ccbf06545a977c9089bcc5a3a81 /src/soc/intel
parent4b966b57edef3a9b4d85abf406d433cfbb415729 (diff)
soc/intel/apollolake: Lock down Global SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/lockdown.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/lockdown.c b/src/soc/intel/apollolake/lockdown.c
index 1b7381da5e..e11778b5dc 100644
--- a/src/soc/intel/apollolake/lockdown.c
+++ b/src/soc/intel/apollolake/lockdown.c
@@ -6,10 +6,17 @@
#include <intelpch/lockdown.h>
#include <soc/pm.h>
+static void pmc_lock_smi(void)
+{
+ uint8_t *pmcbase;
+
+ pmcbase = pmc_mmio_regs();
+
+ setbits32(pmcbase + GEN_PMCON2, SMI_LOCK);
+}
+
void soc_lockdown_config(int chipset_lockdown)
{
- /*
- * Nothing to do here as pmc_global_reset_disable_and_lock
- * is called from chip.c
- */
+ /* APL only supports CHIPSET_LOCKDOWN_COREBOOT */
+ pmc_lock_smi();
}