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authorVarshit B Pandya <varshit.b.pandya@intel.com>2022-03-29 18:16:20 +0530
committerPaul Fagerburg <pfagerburg@chromium.org>2022-04-01 13:45:57 +0000
commitd025ab3bc2e2a9e116bfa43a3abf2f16ed4e7147 (patch)
tree1607941ec0d99e3f725d4aef669f1076f1daa623 /src/soc/intel
parente7d3a1a9e8e69cfa2963339e7cf45160509cd784 (diff)
soc/intel/alderlake: Add HID for DPTF Power Participant
BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/dptf.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c
index 37754dbfae..59243baaeb 100644
--- a/src/soc/intel/alderlake/dptf.c
+++ b/src/soc/intel/alderlake/dptf.c
@@ -12,6 +12,8 @@ static const struct dptf_platform_info adl_dptf_platform_info = {
.fan_hid = "INTC1048",
/* _HID for the toplevel TPCH device, typically \_SB.TPCH */
.tpch_device_hid = "INTC1049",
+ /* _HID for the toplevel TPWR device, typically \_SB.DPTF.TPWR */
+ .tpwr_device_hid = "INTC1060",
.tpch_method_names = {
.set_fivr_low_clock_method = "RFC0",