diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-03-22 15:50:08 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-03-26 04:52:57 +0000 |
| commit | c8ac8f5ce969196f9e38e24629120ab8c5a4c873 (patch) | |
| tree | b05c98e9ea1c3bfac49e92de86faf44544598cd9 /src/soc/intel | |
| parent | 74406e10539336e6eb201e56c4ee559c54973f03 (diff) | |
soc/intel/alderlake: Align RcompResistor definition as per MRC
List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.
Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.
2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.
3. Also, update RcompResistor value for ADLRVP.
BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.
Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/meminit.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/meminit.c | 5 |
2 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index ae86cc6da4..9813d9345e 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -20,11 +20,10 @@ struct mem_ddr_config { /* Dqs Pins Interleaved Setting. Enable/Disable Control */ bool dq_pins_interleaved; /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + * Rcomp resistor value. This values represents the resistance in + * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC. */ - uint16_t rcomp_resistor[3]; + uint16_t rcomp_resistor; /* Rcomp target values. */ uint16_t rcomp_targets[5]; }; diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 5b65ef063f..dcff61113a 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -28,9 +28,8 @@ static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config) { mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved; - memcpy(&mem_cfg->RcompResistor, ddr_config->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); - memcpy(&mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget)); + mem_cfg->RcompResistor = ddr_config->rcomp_resistor; + memcpy(mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget)); } static const struct soc_mem_cfg soc_mem_cfg[] = { |