diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-06-16 09:56:26 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-18 04:40:38 +0000 |
| commit | c57d303f9cf18574370878392986224b57595818 (patch) | |
| tree | 419e210a911036dbc636121500257968750b7b2c /src/soc/intel | |
| parent | 0faba3cf237df532dce8f61ca6a765c335093bbf (diff) | |
soc/intel/car/cache_as_ram.S: Fix typo in comment
Change-Id: Ia91dbda44f60388324cf58dbccdbd2172dbff21d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0d9eb67b94..3817fa5b99 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -36,7 +36,7 @@ clear_fixed_mtrr: post_code(0x22) - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ |