diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-11-04 18:12:58 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-18 23:31:04 +0000 |
| commit | c510346b0803b6888f313bd61ab1ee088135a5c2 (patch) | |
| tree | 563ba342ea10c66a23ff89fa6e601dc8ecde9c56 /src/soc/intel | |
| parent | 570645dc2af26ec26cc8a453f43585bc82fc2521 (diff) | |
soc/intel/alderlake: Add Acoustic noise mitigation UPDs
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate
BUG=b:204009588
TEST=build
Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 14 |
2 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index d2594420c3..78f639cd3b 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -151,6 +151,21 @@ enum fivr_spread_spectrum_ratio { FIVR_SS_6 = 44, }; +/* + * Slew Rate configuration for Deep Package C States for VR domain. + * They are fast time divided by 2. + * 0 - Fast/2 + * 1 - Fast/4 + * 2 - Fast/8 + * 3 - Fast/16 + */ +enum slew_rate { + SLEW_FAST_2, + SLEW_FAST_4, + SLEW_FAST_8, + SLEW_FAST_16 +}; + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -528,6 +543,15 @@ struct soc_intel_alderlake_config { * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. */ uint8_t FivrSpreadSpectrum; + /* Enable or Disable Acoustic Noise Mitigation feature */ + uint8_t AcousticNoiseMitigation; + /* Disable Fast Slew Rate for Deep Package C States for VR domains */ + uint8_t FastPkgCRampDisable[NUM_VR_DOMAINS]; + /* + * Slew Rate configuration for Deep Package C States for VR domains + * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values + */ + uint8_t SlowSlewRate[NUM_VR_DOMAINS]; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 17edada9ba..e43335e467 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -739,6 +739,19 @@ static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; } +static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + + if (s_cfg->AcousticNoiseMitigation) { + for (int i = 0; i < NUM_VR_DOMAINS; i++) { + s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; + s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i]; + } + } +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_alderlake_config *config) { @@ -770,6 +783,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_irq_params, fill_fsps_fivr_params, fill_fsps_fivr_rfi_params, + fill_fsps_acoustic_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |