diff options
| author | Shelley Chen <shchen@chromium.org> | 2018-01-31 15:57:43 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2018-02-06 03:01:01 +0000 |
| commit | c12dff9098fb4023b878102fd5eecdb10c37fcdb (patch) | |
| tree | c78328e56a1cd6d07ab901f95e4d0538915cc70d /src/soc/intel | |
| parent | c4f94b1a7514b58388d347e79575b547eb82d08f (diff) | |
mb/google/fizz: Determine PsysPl3 and Pl4 values
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid
brownouts. According to Intel doc #560604, page 74, the max time
window is 64ms (code=6) and the min duty cycle we can set is 4%.
BUG=b:71594855
BRANCH=None
TEST=Boot to OS and check MSRs using iotools for expected values
Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions