soc/intel/cannonlake: Switch PMC to use device callbacks

Now that the PMC device is marked as hidden in devicetrees, the device
callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks.

Note that this moves PMC initialization from BS_DEV_INIT_CHIPS to
BS_DEV_ENUMERATE, which aligns with other Intel SoCs.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If292728ad975ba803fed6abea879f6f634470a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

5 files changed, 34 insertions, 43 deletions

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index aa6fb1b357..306d8eb6a2 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -195,6 +195,9 @@ static void soc_enable(struct device *dev)
 		dev->ops = &cpu_bus_ops;
 	else if (dev->path.type == DEVICE_PATH_GPIO)
 		block_gpio_enable(dev);
+	else if (dev->path.type == DEVICE_PATH_PCI &&
+		 dev->path.pci.devfn == PCH_DEVFN_PMC)
+		dev->ops = &pmc_ops;
 }
 
 struct chip_operations soc_intel_cannonlake_ops = {
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 7b00398a36..c8120a917e 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -3,6 +3,10 @@
 #ifndef _SOC_CANNONLAKE_PMC_H_
 #define _SOC_CANNONLAKE_PMC_H_
 
+#include <device/device.h>
+
+extern struct device_operations pmc_ops;
+
 /* PCI Configuration Space (D31:F2): PMC */
 #define  PWRMBASE		0x10
 #define  ABASE			0x20
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 0e63e0dc97..315b704fb3 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -49,21 +49,4 @@ void lpc_soc_init(struct device *dev)
 	i8259_configure_irq_trigger(9, 1);
 }
 
-/* Fill up LPC IO resource structure inside SoC directory */
-void pch_lpc_soc_fill_io_resources(struct device *dev)
-{
-	/*
-	 * PMC pci device gets hidden from PCI bus due to Silicon
-	 * policy hence bind ACPI BASE aka ABASE (offset 0x20) with
-	 * LPC IO resources to ensure that ABASE falls under PCI reserved
-	 * IO memory range.
-	 *
-	 * Note: Don't add any more resource with same offset 0x20
-	 * under this device space.
-	 */
-	pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4,
-			ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO |
-			IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
-}
-
 #endif
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index d6c30a8b9e..59f4be5564 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -68,7 +68,22 @@ static void config_deep_sx(uint32_t deepsx_config)
 	write32(pmcbase + DSX_CFG, reg);
 }
 
-static void pmc_init(void *unused)
+static void soc_pmc_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Add the fixed MMIO resource */
+	mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+
+	/* Add the fixed I/O resource */
+	res = new_resource(dev, 1);
+	res->base = (resource_t)ACPI_BASE_ADDRESS;
+	res->size = (resource_t)ACPI_BASE_SIZE;
+	res->limit = res->base + res->size - 1;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void pmc_init(struct device *dev)
 {
 	const config_t *config = config_of_soc();
 
@@ -82,16 +97,7 @@ static void pmc_init(void *unused)
 	config_deep_sx(config->deep_sx_config);
 }
 
-/*
-* Initialize PMC controller.
-*
-* PMC controller gets hidden from PCI bus during FSP-Silicon init call.
-* Hence PCI enumeration can't be used to initialize bus device and
-* allocate resources.
-*/
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
-
-static void soc_acpi_mode_init(void *unused)
+static void soc_acpi_mode_init(struct device *dev)
 {
 	/*
 	 * PMC initialization happens earlier for this SoC because FSP-Silicon
@@ -106,11 +112,17 @@ static void soc_acpi_mode_init(void *unused)
 	 * taking different actions based on disabling of ACPI (e.g. flushing of
 	 * all EC hostevent bits).
 	 *
-	 * P.S.: This cannot be done as part of pmc_soc_init as PMC device is
-	 * hidden and hence the PMC driver never gets enumerated and so init is
-	 * not called for it.
+	 * Because the device is set as `hidden` in the devicetree, enumeration
+	 * is skipped, but the device callbacks are still called as if it were
+	 * found.
 	 */
 	pmc_set_acpi_mode();
 }
 
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_acpi_mode_init, NULL);
+struct device_operations pmc_ops = {
+	.read_resources	  = soc_pmc_read_resources,
+	.set_resources	  = noop_set_resources,
+	.init		  = soc_acpi_mode_init,
+	.enable		  = pmc_init,
+	.scan_bus	  = scan_static_bus,
+};
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c
index a79e618dbd..0b5e8e3f95 100644
--- a/src/soc/intel/cannonlake/systemagent.c
+++ b/src/soc/intel/cannonlake/systemagent.c
@@ -27,17 +27,6 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 		{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
 		{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
 		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
-		/*
-		 * PMC pci device gets hidden from PCI bus due to Silicon
-		 * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
-		 * SA resources to ensure that PMCBAR falls under PCI reserved
-		 * memory range.
-		 *
-		 * Note: Don't add any more resource with same offset 0x10
-		 * under this device space.
-		 */
-		{ PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
-				"PMCBAR" },
 	};
 
 	sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,