diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-12-28 10:32:50 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-29 16:35:57 +0000 |
| commit | bd0fa62b6be176395dc119099236709e52a6203e (patch) | |
| tree | 9b67442fbea963ebb1c225532ddf7106a1e8872f /src/soc/intel | |
| parent | dcbb87a3ecca3e056a01b0231c52eeb70ff716ea (diff) | |
soc/intel/skylake: Add 4 missing root ports to chipset dt
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing
root ports to the chipset devicetree.
Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48947
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chipset.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 136630efa9..28ee53d3ad 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -31,6 +31,10 @@ chip soc/intel/skylake device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18 device pci 1b.2 alias pcie_rp19 off end # PCI Express Port 19 device pci 1b.3 alias pcie_rp20 off end # PCI Express Port 20 + device pci 1b.4 alias pcie_rp21 off end # PCI Express Port 21 + device pci 1b.5 alias pcie_rp22 off end # PCI Express Port 22 + device pci 1b.6 alias pcie_rp23 off end # PCI Express Port 23 + device pci 1b.7 alias pcie_rp24 off end # PCI Express Port 24 device pci 1c.0 alias pcie_rp1 off end # PCI Express Port 1 device pci 1c.1 alias pcie_rp2 off end # PCI Express Port 2 device pci 1c.2 alias pcie_rp3 off end # PCI Express Port 3 |