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authorSubrata Banik <subrata.banik@intel.com>2021-11-17 15:35:05 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-11-20 17:49:25 +0000
commitb2e8bd83647f664260120fdfc7d07cba694dd89e (patch)
tree4ed4903ef9ea0cd95c0b224d20220d6bd9d18960 /src/soc/intel
parent8c45f236bc74a12819c4bc09a4b3e6d52bee3066 (diff)
soc/intel/alderlake: Hook up common code for thermal configuration
Thermal configuration registers are now located behind PMC PWRMBASE for Alder Lake Point PCH. Hence, ADL SoC to select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold is being set as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. BUG=b:193774296 TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59271 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/Kconfig1
-rw-r--r--src/soc/intel/alderlake/romstage/romstage.c11
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 58b9051e6d..2cbff0010d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -68,6 +68,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_TCSS
+ select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index d7ef14d11f..e84eca8ed4 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -8,6 +8,7 @@
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h>
+#include <intelblocks/thermal.h>
#include <memory_info.h>
#include <soc/intel/common/smbios.h>
#include <soc/iomap.h>
@@ -127,6 +128,16 @@ void mainboard_romstage_entry(void)
heci_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
+
+ /*
+ * Set low maximum temp threshold value used for dynamic thermal sensor
+ * shutdown consideration.
+ *
+ * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+ * thermal sensor when CPU is in a C-state and LTT >= DTS Temp.
+ */
+ pch_thermal_configuration();
+
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake) {