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authorWon Chung <wonchung@google.com>2023-04-10 20:52:55 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-05-08 13:12:41 +0000
commitaf879f2d34207b99bbb62e49a6e1bdcec4e217f4 (patch)
treebcc27d4ed9446d5fb67d69a0bab8bc8bebcf67a4 /src/soc/intel
parent467c88b3a971a364d2013b9e397d9cd6f5bcfdda (diff)
mb/google/rex/var/rex0: Correct _PLD values for USB C0
Denote the correct value of ACPI _PLD for USB ports. The horizontal position of port C0 is incorrectly labelled. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
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