diff options
| author | Jakub Czapiga <jacz@semihalf.com> | 2022-02-15 11:50:31 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-08 16:06:33 +0000 |
| commit | ad6157ebdfddc39b95e388487e00cadd2bbf368b (patch) | |
| tree | bbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/soc/intel | |
| parent | e96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff) | |
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/raminit.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_eop.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index ae83d49275..9720d9e549 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -137,9 +137,9 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { - timestamp_add_now(TS_START_CSE_FW_SYNC); + timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); - timestamp_add_now(TS_END_CSE_FW_SYNC); + timestamp_add_now(TS_CSE_FW_SYNC_END); } /* diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index dbf4afc17a..74238e2721 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -101,7 +101,7 @@ void mainboard_romstage_entry(void) memset(&mp, 0, sizeof(mp)); mainboard_fill_mrc_params(&mp); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); ps = fill_power_state(); prev_sleep_state = chipset_prev_sleep_state(ps); @@ -115,7 +115,7 @@ void mainboard_romstage_entry(void) /* Initialize RAM */ raminit(&mp, prev_sleep_state); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); romstage_handoff_init(s3resume); } diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 28b3f37ed9..95073d3194 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -188,14 +188,14 @@ void perform_raminit(const struct chipset_power_state *const power_state) post_code(0x32); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); pei_data.boot_mode = power_state->prev_sleep_state; /* Initialize RAM */ sdram_initialize(&pei_data); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); int cbmem_was_initted = !cbmem_recovery(s3resume); if (s3resume && !cbmem_was_initted) { diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 3a08a7381c..af6abb8060 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -192,9 +192,9 @@ static void do_send_end_of_post(void) set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); - timestamp_add_now(TS_ME_BEFORE_END_OF_POST); + timestamp_add_now(TS_ME_END_OF_POST_START); handle_cse_eop_result(cse_send_eop()); - timestamp_add_now(TS_ME_AFTER_END_OF_POST); + timestamp_add_now(TS_ME_END_OF_POST_END); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); |