diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-30 15:46:07 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-27 06:34:41 +0100 |
| commit | a8e9b63166876941d1d8e54b732d824a8ef38a76 (patch) | |
| tree | 802fbcca396fddffc8f08af272e6ded0f39cbcad /src/soc/intel | |
| parent | 6e77beec96b538f26c63f2623c72a7e5d24fb5e1 (diff) | |
baytrail: increment boot count for elog
The elog boot counter in cmos was not being initialized
nor incremented. Start doing that in romstage. Since S3
resume is not detected yet the increment is unconditional.
BUG=None
BRANCH=None
TEST=Built and booted through depthcharge multiple times. Noted
output such as 'Boot Count incremented to 4'.
Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174717
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4919
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 9752363cfd..5af9bf4566 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -28,6 +28,7 @@ #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> #endif +#include <elog.h> #include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> @@ -145,6 +146,10 @@ void romstage_common(struct romstage_params *params) mark_ts(params, timestamp_get()); +#if CONFIG_ELOG_BOOT_COUNT + boot_count_increment(); +#endif + /* Initialize RAM */ raminit(params->mrc_params, 5); |