diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-05-18 22:24:17 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2022-11-02 18:43:38 +0000 |
| commit | 9c2d8135fe7bcff50462f8aa216b34ff2793aa59 (patch) | |
| tree | 43529e11a8731dc39381235e61159e7e78e2f633 /src/soc/intel | |
| parent | 1a52a4fe51a61297cfe18aa7307d330076d3a6aa (diff) | |
soc/intel/common/acpi: provide PTS/WAK hooks for ECs
Provide PTS/WAK hooks for ECs like we do for mainboards.
Change-Id: I687254362a896baa590959bd01ae49579ec12c94
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68788
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/acpi/platform.asl | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index c988e0a43f..6a19792bf4 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -6,6 +6,8 @@ External(\_SB.MPTS, MethodObj) External(\_SB.MWAK, MethodObj) External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) +External(\_SB.PCI0.LPCB.EC0.PTS, MethodObj) +External(\_SB.PCI0.LPCB.EC0.WAK, MethodObj) #include <arch/x86/acpi/post.asl> @@ -18,6 +20,10 @@ Method (_PTS, 1) { DBG0 = POST_OS_ENTER_PTS + If (CondRefOf (\_SB.PCI0.LPCB.EC0.PTS)) + { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + } If (CondRefOf (\_SB.MPTS)) { \_SB.MPTS (Arg0) @@ -38,6 +44,10 @@ Method (_WAK, 1) { DBG0 = POST_OS_ENTER_WAKE + If (CondRefOf (\_SB.PCI0.LPCB.EC0.WAK)) + { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) + } If (CondRefOf (\_SB.MWAK)) { \_SB.MWAK (Arg0) |