diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-26 14:23:12 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-10-16 09:29:38 +0000 |
| commit | 9c19bf090e8a1bd69c7fd52188adaa956d65c9a2 (patch) | |
| tree | c1bd907436667c536bc11293e686562b9af7f68f /src/soc/intel | |
| parent | c47fc4002261e241890c098335eaaf4cb51c844a (diff) | |
soc/intel/dnv_ns: enable uCode PM Timer emulation
Denverton-NS supports uCode PM Timer emulation, according to Intel
doc#558579 rev2.2. Thus, enable it.
Change-Id: I21f55816da9f5e240fdf01a0e92b67b09ef38599
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index c657285a25..a578a71fd0 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES + select CPU_SUPPORTS_PM_TIMER_EMULATION select DEBUG_GPIO select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 95f164d1c5..60635483d4 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -94,6 +94,8 @@ static void denverton_core_init(struct device *cpu) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); + + enable_pm_timer_emulation(); } static struct device_operations cpu_dev_ops = { |