diff options
| author | John Zhao <john.zhao@intel.com> | 2020-05-19 11:10:21 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:02:16 +0000 |
| commit | 7d054bd38f5cfe36f6abd4f4422c463243bc3749 (patch) | |
| tree | 3babb7b0e12f0bd89e332516fd35c35f34050a2e /src/soc/intel | |
| parent | e6e9fa6ef90bc62d645da942f3bdc7bdeb1c1930 (diff) | |
soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method
CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation
region to be SystemIO and ACPI_BASE_ADDRESS.
BUG=b:156530805
TEST=Built and booted to kernel.
Signed-off-by: John zhao <john.zhao@intel.com>
Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 7d586dd11e..abdcb515fa 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -45,10 +45,10 @@ Scope (\_SB) } /* - * Define PCH ACPIBASE as an ACPI operating region. The base address can be + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. */ - OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80) + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ , 19, |