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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2017-10-11 11:40:08 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-20 20:05:53 +0000
commit771d4833d12da75cd95efbf979b3f2ac3bb6e8d7 (patch)
treebf74f17eab07e9e810c6351da4c47f3c400eec2b /src/soc/intel
parentba142c5ef07dcea4e41b98867dd56c4d76744788 (diff)
intel/common/acpi: Add common SGX ASL
- Add EPC device for SGX. Kernel SGX driver expects EPC device. - Hid is INT0E0C - version of the object is 1.0, so _STR is "Enclave Page Cache 1.0" Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/acpi/sgx.asl73
1 files changed, 73 insertions, 0 deletions
diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl
new file mode 100644
index 0000000000..43de44f33c
--- /dev/null
+++ b/src/soc/intel/common/acpi/sgx.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+External(\_SB.EPCS, IntObj) // Enclave Page Cache (EPC) Status
+External(\_SB.EMNA, IntObj) // EPC base address
+External(\_SB.ELNG, IntObj) // EPC length
+
+Scope(\_SB)
+{
+ // Secure Enclave memory
+ Device (EPC)
+ {
+ Name (_HID, EISAID ("INT0E0C"))
+ Name (_STR, Unicode ("Enclave Page Cache 1.0"))
+ Name (_MLS, Package () {
+ Package (2) { "en", Unicode ("Enclave Page Cache 1.0") }
+ })
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ // _MIN, _MAX and _LEN get patched runtime
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN
+ 0, // AddressMaximum _MAX
+ 0, // AddressTranslation _TRA
+ 1, // RangeLength _LEN
+ , // ResourceSourceIndex
+ , // ResourceSource
+ BAR0 // DescriptorName
+ )
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateQwordField (RBUF, ^BAR0._MIN, EMIN)
+ CreateQwordField (RBUF, ^BAR0._MAX, EMAX)
+ CreateQwordField (RBUF, ^BAR0._LEN, ELEN)
+ Store (\_SB.EMNA, EMIN)
+ Store (\_SB.ELNG, ELEN)
+ Subtract (Add (\_SB.EMNA, \_SB.ELNG), 1, EMAX)
+ Return (RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ If (LNotEqual (\_SB.EPCS, 0))
+ {
+ Return (0xF)
+ }
+ Return (0x0)
+ }
+
+ } // end EPC Device
+} // End of Scope(\_SB)