diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-01 08:25:11 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 21:54:01 +0000 |
| commit | 72d94026ce6ec2c6b363b70652e97c0041a70776 (patch) | |
| tree | 0395968e550d7d3df8ef7c5c008f4085b08656db /src/soc/intel | |
| parent | 90f9cbbfc4ae1f03028176b124c2be54e579fd3f (diff) | |
soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch tigerlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pmc.c | 14 |
3 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 4ae25f0366..00913c7e64 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -48,6 +48,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 3d718b2ccb..83453e2633 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -42,8 +42,5 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index dd2b61b3c0..426d8a9ce9 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -11,10 +11,12 @@ #include <device/mmio.h> #include <device/device.h> #include <drivers/intel/pmc_mux/chip.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/pmc_ipc.h> #include <intelblocks/rtc.h> +#include <soc/lpm.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> @@ -121,6 +123,18 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) { + const struct soc_pmc_lpm tgl_pmc_lpm = { + .num_substates = 8, + .num_req_regs = 6, + .lpm_ipc_offset = 0x1000, + .req_reg_stride = 0x30, + .lpm_enable_mask = get_supported_lpm_mask(config_of_soc()), + }; + + generate_acpi_power_engine_with_lpm(&tgl_pmc_lpm); + } + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, dev_path(dev)); } |