summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2021-06-14 13:53:44 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2023-05-23 08:25:00 +0000
commit6c42d14d45974fa5a1b08bbd3c48d8fa7945c4ee (patch)
treebe6c1da0409265aed167cb3290db5d574f85f7ac /src/soc/intel
parent8a2c36467c259c965d9b7fbd24352deadf6a0a07 (diff)
nb/intel/haswell: Allow using Broadwell MRC.bin
This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell non-ULT CPUs (for which more magic is required). Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that the system remains on after 30 seconds. Apparently, something Broadwell MRC.bin does results in the ME being unhappy, as there is no such issue when not using MRC.bin at all (native RAM init). S3 resume is working. Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions