diff options
| author | Eran Mitrani <mitrani@google.com> | 2022-06-17 16:19:38 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-23 17:43:00 +0000 |
| commit | 68033c2483e8c639641775acd486bc8fccc2a395 (patch) | |
| tree | afc157ab16b8b79abfefe539bbe05bbaa3f105a6 /src/soc/intel | |
| parent | f23cf44c4715575ffdac41ad3ae0a5f65626ef09 (diff) | |
soc/intel/adl: Cast size in systemagent.c to fix overflow
This CL fixes my previous CL (commit ca741055e)
which introduced a couple of issues found by Coverity (see below).
The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)."
*** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size()
*** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size()
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/systemagent.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 05de0ccfbe..263c5f50ca 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -267,7 +267,7 @@ uint64_t get_dsm_size(struct device *dev) if (size_field <= 0x10) { // 0x0 - 0x10 size = size_field * 32 * MiB; } else if ((size_field >= 0xF0) && (size_field >= 0xFE)) { - size = (size_field - 0xEF) * 4 * MiB; + size = ((uint64_t)size_field - 0xEF) * 4 * MiB; } else { switch (size_field) { case 0x20: @@ -318,6 +318,6 @@ uint64_t get_dpr_size(struct device *dev) uint64_t size; uint32_t dpr_reg = pci_read_config32(dev, DPR_REG); uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB; - size = size_field * MiB; + size = (uint64_t)size_field * MiB; return size; } |