diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-24 16:43:21 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-27 22:45:20 +0000 |
| commit | 643c82e9968e7ca7cfc2454e11c193a845f874ea (patch) | |
| tree | 8ba8051d16707842628995c35beea74c2479fd80 /src/soc/intel | |
| parent | 666c4caccb2b50781f5de3044ae4b51e4c0e2960 (diff) | |
soc/intel/*/chip.h: Use `uint32_t` for `tcc_offset`
Newer platforms use an unsigned type instead of an int. Follow suit.
Change-Id: I316864d3aed203c7c2bc962772895774fbc0c8da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 521d3ee06c..6e4c82d5a4 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -124,7 +124,7 @@ struct soc_intel_apollolake_config { int dptf_enable; /* TCC activation offset value in degrees Celsius */ - int tcc_offset; + uint32_t tcc_offset; /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index f559410c57..ae433536cd 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -138,7 +138,7 @@ struct soc_intel_broadwell_config { int deep_sx_enable_dc; /* TCC activation offset */ - int tcc_offset; + uint32_t tcc_offset; }; typedef struct soc_intel_broadwell_config config_t; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a623292446..fa30c1dfcf 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -85,7 +85,7 @@ struct soc_intel_skylake_config { uint32_t deep_sx_config; /* TCC activation offset */ - int tcc_offset; + uint32_t tcc_offset; /* Package PL4 power limit in Watts */ u32 PowerLimit4; |