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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-05-04 19:04:33 +0200 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-17 19:46:30 +0000 |
| commit | 62d42c3266a633cd11009148522b4adb2542976e (patch) | |
| tree | d5c55ab2297651c1b7b09325e4efdc0567e5b348 /src/soc/intel | |
| parent | 9022344cde972437f14a8516abd7354acbdad136 (diff) | |
soc/amd/common/include/espi: add more decode ranges
Mendocino has more eSPI decode ranges than Picasso or Cezanne. To
support these additional ranges, introduce a new Kconfig option
SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by
the SoCs that support the additional eSPI IO/MMIO decode ranges.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions