diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-03-12 18:28:03 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-17 08:01:14 +0000 |
| commit | 61dd05e010d91447eafff11cd65baab4e21e0bdb (patch) | |
| tree | 0bd58dc3ca3e27bd80e645a6f7a0418d6cde6cb7 /src/soc/intel | |
| parent | 4248d8e7bb1934979a2fc1b4479429a068f0441f (diff) | |
soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstage
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
Test=Verified on Alderlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index cc3126bb41..d7ef14d11f 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -129,6 +129,15 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } } |