diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-04-20 11:08:17 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 15:23:13 +0000 |
| commit | 5ff0118a58a6ff67f0e89920403738e77e302d74 (patch) | |
| tree | bcbf12c593986e3db83f854df908c356cecf8d01 /src/soc/intel | |
| parent | db7b35a9c97c07a6097779459a7816c38242f569 (diff) | |
soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function
This patch refactors cse_fw_sync() function to include timestamp
associated with the CSE sync operation.This effort will ensure the
SoC code just makes a call into the cse_fw_sync() without bothering
about adding timestamp entries.
TEST=Able to build and boot google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/romstage.c | 5 |
3 files changed, 11 insertions, 13 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index a3273e610a..740a4a2806 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -180,11 +180,8 @@ void mainboard_romstage_entry(void) if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1e2a052378..14a73814bf 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1077,7 +1077,7 @@ static enum csme_failure_reason cse_sub_part_fw_update(const struct cse_bp_info return handle_cse_sub_part_fw_update_rv(rv); } -void cse_fw_sync(void) +static void do_cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; @@ -1152,6 +1152,13 @@ void cse_fw_sync(void) } } +void cse_fw_sync(void) +{ + timestamp_add_now(TS_CSE_FW_SYNC_START); + do_cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); +} + static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1214,11 +1221,8 @@ static void ramstage_cse_fw_sync(void *unused) if (acpi_get_sleep_type() == ACPI_S3) return; - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_fw_sync, NULL); diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index ebb440c5f9..b5351de2b7 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -128,11 +128,8 @@ void mainboard_romstage_entry(void) /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); - if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { - timestamp_add_now(TS_CSE_FW_SYNC_START); + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) cse_fw_sync(); - timestamp_add_now(TS_CSE_FW_SYNC_END); - } /* Update coreboot timestamp table with CSE timestamps */ if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) |