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| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-02-02 13:04:33 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-03 17:27:30 +0000 |
| commit | 4c4a360018315b3bd60d3cfc3506137a631ee7ba (patch) | |
| tree | 76c93db60b686ea263ff0af6a0a87ed9e72f4617 /src/soc/intel | |
| parent | 275440edf1107143865413631efc3f6aace4e7a5 (diff) | |
soc/amd/picasso: clean up and re-sort UPD table
Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.
remove:
EDpPhySel
EDpVersion
rename:
DpPhyOverride -> edp_phy_override
EDpPhySel -> edp_physel
DpVsPemphLevel -> edp_dp_vs_pemph_level
MarginDeemPh -> edp_margin_deemph
Deemph6db4 -> edp_deemph_6db_4
BoostAdj -> edp_boost_adj
eDP phy setting:
DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004b
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions