soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE

In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to
programming PWRMBASE and enable BIT 2 after programming PWRMBASE
along with PCI_COMMAND_MEMORY (BIT 1).

Also perform below operations
1. Use pci_and_config16 instead of pci read and write
2. Use setbits32 instead of mmio read and write

Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

4 files changed, 16 insertions, 40 deletions

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index ae52f45454..e1f054857a 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -59,26 +59,20 @@ static uint32_t get_pmc_reg_base(void)
 
 static void soc_config_pwrmbase(void)
 {
-	uint32_t reg32;
-	uint16_t reg16;
-
 	/*
 	 * Assign Resources to PWRMBASE
-	 * Clear BIT 1-2  Command Register
+	 * Clear BIT 1-2 Command Register
 	 */
-	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
+	pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Program PWRM Base */
 	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
 
 	/* Enable Bus Master and MMIO Space */
-	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Enable PWRM in PMC */
-	reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
-	write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
+	setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
 }
 
 void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 6ebf9101b3..f36bd31e3b 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -40,26 +40,20 @@
 
 static void soc_config_pwrmbase(void)
 {
-	uint32_t reg32;
-	uint16_t reg16;
-
 	/*
 	 * Assign Resources to PWRMBASE
-	 * Clear BIT 1-2  Command Register
+	 * Clear BIT 1-2 Command Register
 	 */
-	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
+	pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Program PWRM Base */
 	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
 
 	/* Enable Bus Master and MMIO Space */
-	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Enable PWRM in PMC */
-	reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
-	write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
+	setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
 }
 
 void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index 1260bc8c07..f59d9c909f 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -44,26 +44,20 @@
 
 static void soc_config_pwrmbase(void)
 {
-	uint32_t reg32;
-	uint16_t reg16;
-
 	/*
 	 * Assign Resources to PWRMBASE
-	 * Clear BIT 1-2  Command Register
+	 * Clear BIT 1-2 Command Register
 	 */
-	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
+	pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Program PWRM Base */
 	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
 
 	/* Enable Bus Master and MMIO Space */
-	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Enable PWRM in PMC */
-	reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
-	write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
+	setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
 }
 
 void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 9fc5ce167b..63beeaa601 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -49,26 +49,20 @@
 
 static void soc_config_pwrmbase(void)
 {
-	uint32_t reg32;
-	uint16_t reg16;
-
 	/*
 	 * Assign Resources to PWRMBASE
-	 * Clear BIT 1-2  Command Register
+	 * Clear BIT 1-2 Command Register
 	 */
-	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
-	reg16 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
+	pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Program PWRM Base */
 	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
 
 	/* Enable Bus Master and MMIO Space */
-	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 
 	/* Enable PWRM in PMC */
-	reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
-	write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
+	setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
 }
 
 void bootblock_pch_early_init(void)