soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 26 insertions, 14 deletions

diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 31ea8657ee..1377fff9e0 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -22,6 +22,7 @@ bootblock-y += p2sb.c
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
+romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -35,6 +36,7 @@ ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += systemagent.c
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index 7b185c3e64..184e6ed4c7 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -14,14 +14,10 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 
-static const struct pcie_rp_group pch_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,    .count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 66ad223167..af7ee54188 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -146,7 +146,6 @@ struct soc_intel_jasperlake_config {
 	bool PchHdaIDispCodecDisconnect;
 
 	/* PCIe Root Ports */
-	bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
diff --git a/src/soc/intel/jasperlake/include/soc/pcie.h b/src/soc/intel/jasperlake/include/soc/pcie.h
new file mode 100644
index 0000000000..17710cc808
--- /dev/null
+++ b/src/soc/intel/jasperlake/include/soc/pcie.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_JASPERLAKE_PCIE_H__
+#define __SOC_JASPERLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+extern const struct pcie_rp_group pch_rp_groups[];
+
+#endif /* __SOC_JASPERLAKE_PCIE_H__ */
diff --git a/src/soc/intel/jasperlake/pcie_rp.c b/src/soc/intel/jasperlake/pcie_rp.c
new file mode 100644
index 0000000000..844cc544c5
--- /dev/null
+++ b/src/soc/intel/jasperlake/pcie_rp.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+const struct pcie_rp_group pch_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,    .count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 43a8c7003f..0132906534 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -5,8 +5,10 @@
 #include <device/device.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 
@@ -14,7 +16,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_jasperlake_config *config)
 {
 	unsigned int i;
-	uint32_t mask = 0;
 
 	/*
 	 * If IGD is enabled, set IGD stolen size to 60MB.
@@ -61,13 +62,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		}
 	}
 
-	/* PCIe root port configuration */
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-
-	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
 
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);