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authorDuncan Laurie <dlaurie@chromium.org>2018-03-02 14:39:47 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-03-06 08:46:37 +0000
commit3879ef49ea4dd2186614295f4aeb9e43c252b553 (patch)
tree1470476dfb97b7a9f7b189cb111cc83f595e58e4 /src/soc/intel
parent069ca66ea402b51e2043a5587f29819e9331e8bf (diff)
mb/google/fizz: Skip FSP init for UART 0
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. coreboot is setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device. The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots. Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
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