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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-04 17:31:10 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-06 18:59:27 +0000 |
| commit | 2f5c7590770f7bbb00f899a1495675083872b0d7 (patch) | |
| tree | 50e46daaae55446be9dd84c8360c80b52d71d547 /src/soc/intel | |
| parent | 0a93f7a7e99bf0872e019adeed08bf7b620a8985 (diff) | |
soc/amd: factor out common family 17h&19h TSC and monotonic timer code
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions