diff options
| author | Selma Bensaid <selma.bensaid@intel.com> | 2021-10-11 16:37:36 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-15 00:15:07 +0000 |
| commit | 291294d137393bb1f4d59b388f287134943f2a95 (patch) | |
| tree | d3cf347ef6ac75f7bb52376604bcc54084ab4c8e /src/soc/intel | |
| parent | c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d (diff) | |
soc/intel/alderlake: fix NULL pointer dereference
microcode_file could be NULL and passed to get_microcode_size,
this was detected by klocwork scan.
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 333957f2ea..f9569f9e41 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -346,12 +346,14 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, /* Locate microcode and pass to FSP-S for 2nd microcode loading */ microcode_file = intel_microcode_find(); - microcode_len = get_microcode_size(microcode_file); - if ((microcode_file != NULL) && (microcode_len != 0)) { - /* Update CPU Microcode patch base address/size */ - s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; - s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + if (microcode_file != NULL) { + microcode_len = get_microcode_size(microcode_file); + if (microcode_len != 0) { + /* Update CPU Microcode patch base address/size */ + s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; + s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + } } /* Use coreboot MP PPI services if Kconfig is enabled */ |