diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-07 15:03:09 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-03 19:36:42 +0000 |
| commit | 27fdfc60bc3b5ab1c2e59599d54093bbb25d37a7 (patch) | |
| tree | fc398b74615479f0f6a7b8fae1b10bea226d906b /src/soc/intel | |
| parent | 86221c63aefeec10571a4698e74737af80c0539f (diff) | |
soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.
Based on the Intel DOC #619501 and #619362.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4ab58d4ea7..1507d6f235 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -212,16 +212,17 @@ config MAX_PCH_ROOT_PORTS default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 if SOC_INTEL_ALDERLAKE_PCH_N default 12 if SOC_INTEL_ALDERLAKE_PCH_P + default 28 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 0 if SOC_INTEL_ALDERLAKE_PCH_N - default 3 if SOC_INTEL_ALDERLAKE_PCH_P + default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S config MAX_TBT_ROOT_PORTS int - default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S default 2 if SOC_INTEL_ALDERLAKE_PCH_M default 4 if SOC_INTEL_ALDERLAKE_PCH_P @@ -234,12 +235,14 @@ config MAX_PCIE_CLOCK_SRC default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 7 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_PCIE_CLOCK_REQ int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config SMM_TSEG_SIZE hex |