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authorSubrata Banik <subrata.banik@intel.com>2017-07-17 16:52:15 +0530
committerAaron Durbin <adurbin@chromium.org>2017-07-21 14:44:22 +0000
commitba3ae3eead28d1fbae0527abca091a01b6876cb6 (patch)
tree30ce1d67448f611369d43c52cd814d47ccb5a3a1 /src/soc/intel
parent3ff14a0c8590705ba4cc184f6e9d6e5f6302fb4c (diff)
soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/include/soc/lpc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h
index b46b8ca5ca..f3541a07c6 100644
--- a/src/soc/intel/skylake/include/soc/lpc.h
+++ b/src/soc/intel/skylake/include/soc/lpc.h
@@ -51,7 +51,7 @@
#define LGMR 0x98 /* LPC Generic Memory Range */
#define BIOS_CNTL 0xdc
#define LPC_BC_BILD (1 << 7) /* BILD */
-#define LPC_BC_LE (1 << 2) /* LE */
+#define LPC_BC_LE (1 << 1) /* LE */
#define LPC_BC_EISS (1 << 5) /* EISS */
#define PCCTL 0xE0 /* PCI Clock Control */
#define CLKRUN_EN (1 << 0)