From ba3ae3eead28d1fbae0527abca091a01b6876cb6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 17 Jul 2017 16:52:15 +0530 Subject: soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definition LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/include/soc/lpc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h index b46b8ca5ca..f3541a07c6 100644 --- a/src/soc/intel/skylake/include/soc/lpc.h +++ b/src/soc/intel/skylake/include/soc/lpc.h @@ -51,7 +51,7 @@ #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -- cgit v1.2.3