diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-04-10 10:33:05 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-04-10 18:08:05 +0000 |
| commit | e09ba47b8ba213e9a9d17c3fc0defb857e415100 (patch) | |
| tree | 6ccc983ca222bcd0d44fb5298ecbce4612d86813 /src/soc/intel | |
| parent | 551e4be7301eca04104c8f0d4379b906dfb07c1b (diff) | |
soc/intel/cannonlake: Set Cannonlake I2C clock
Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.
BUG=b:75306520
Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6f4029509c..541e5165af 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -192,7 +192,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + default 133 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int |