From e09ba47b8ba213e9a9d17c3fc0defb857e415100 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Tue, 10 Apr 2018 10:33:05 -0700
Subject: soc/intel/cannonlake: Set Cannonlake I2C clock

Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.

BUG=b:75306520

Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/cannonlake/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/intel')

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 6f4029509c..541e5165af 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -192,7 +192,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
-	default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
+	default 133
 
 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int
-- 
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