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authorArthur Heymans <arthur@aheymans.xyz>2021-09-07 14:16:50 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-09-23 06:38:52 +0000
commitffa61b0f60d8e988a72ea8d2777b9efa6c35d304 (patch)
tree72d69dd44f2e7c987263dc4b9d51c1b9a1aaebd2 /src/soc/intel/xeon_sp
parenta767a148783cea4dad1bf1a4b826debd30c0252e (diff)
soc/intel/xeon_sp/cpx: Use FSP repo
Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/xeon_sp')
-rw-r--r--src/soc/intel/xeon_sp/cpx/Kconfig8
-rw-r--r--src/soc/intel/xeon_sp/cpx/Makefile.inc1
2 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 4e3a7967fc..3c879438a6 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -4,11 +4,13 @@ if SOC_INTEL_COOPERLAKE_SP
config SOC_SPECIFIC_OPTIONS
def_bool y
+ select HAVE_INTEL_FSP_REPO
config FSP_HEADER_PATH
- string "Location of FSP headers"
- depends on MAINBOARD_USES_FSP2_0
- default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"
+ default "3rdparty/fsp/CedarIslandFspBinPkg/Include"
+
+config FSP_FD_PATH
+ default "3rdparty/fsp/CedarIslandFspBinPkg/Fsp.fd"
config MAX_SOCKET
int
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc
index 67d7584ac5..2df370ae2b 100644
--- a/src/soc/intel/xeon_sp/cpx/Makefile.inc
+++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc
@@ -16,6 +16,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp
CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h