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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-03-05 11:54:47 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-30 09:42:55 +0000 |
| commit | e5565c45cb71df105bc9ff1dc7572b4e749adaea (patch) | |
| tree | e000066c58d5c33bd6ec73fef90bc83f25a78213 /src/soc/intel/xeon_sp | |
| parent | 991ee05de9fedc15f178660e0cac0b46e783525e (diff) | |
soc/intel/{icelake, tigerlake}: Remove DDI A lane programming
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
default. And kernel driver no longer relies on coreboot to provide
information via DDI_BUF_CTL_A(for DDI port A) register programming.
Hence removing this code.
BUG=b:150788968
BRANCH=None
TEST=checked jslrvp and tglrvp compilation and boot.
Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
0 files changed, 0 insertions, 0 deletions