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| author | Anand Vaikar <a.vaikar2021@gmail.com> | 2024-01-05 14:27:02 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-15 13:17:33 +0000 |
| commit | d873d3a7ec6d39a792fc08bab4f24d7957866609 (patch) | |
| tree | 00170e0b5dc60d6f8460315c3190f60ec2da12c3 /src/soc/intel/xeon_sp | |
| parent | cf960a320fa1701430e4424829e3882a5a6578f1 (diff) | |
src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size
The PCIE MMCONFIG base address value and size is updated correctly to
access the PCIE config space registers.
TEST=Verified that PCIE enumeration takes place in boot log
and config space registers are accessible.
Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
0 files changed, 0 insertions, 0 deletions