soc/intel/xeon_sp/skx: Lock all PCU registers

Lock all PCU registers on all sockets. The same code can be found
on CPX, which is basically the same CPU. Once the differences between
CPX and SKX are minimal, the platforms can be merged into one codebase.

Change-Id: I73eaa0905e8a418fc9dfe515c42cd257c041cf61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84843
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 117 insertions, 43 deletions

diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 653f2b1fec..6d1797cc3f 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -3,12 +3,14 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <gpio.h>
 #include <intelblocks/acpi.h>
 #include <soc/acpi.h>
 #include <soc/chip_common.h>
 #include <soc/numa.h>
 #include <soc/pch.h>
+#include <soc/pci_devs.h>
 #include <soc/soc_pch.h>
 #include <soc/ramstage.h>
 #include <soc/soc_util.h>
@@ -36,25 +38,79 @@ static void soc_enable_dev(struct device *dev)
 	}
 }
 
-static void soc_init(void *data)
+static void set_pcu_locks(void)
 {
-	printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
-	fsp_silicon_init();
+	struct device *dev = NULL;
 
-	setup_pds();
-	attach_iio_stacks();
+	while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
+		printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+		pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK);
+		pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR,
+				PKG_PWR_LIM_LOCK_UPR);
+		pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO,
+				TURBO_ACTIVATION_RATIO_LOCK);
+	}
 
-	override_hpet_ioapic_bdf();
-	pch_lock_dmictl();
+	dev = NULL;
+	while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
+		printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+		pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK);
+	}
+
+	dev = NULL;
+	while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) {
+		printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+		pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT,
+				PP_PWR_LIM_LOCK);
+		pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR,
+				DRAM_POWER_INFO_LOCK_UPR);
+	}
+
+	dev = NULL;
+	while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) {
+		printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev));
+		pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK);
+		pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK);
+	}
+}
+
+static void set_imc_locks(void)
+{
+	struct device *dev = 0;
+	while ((dev = dev_find_device(PCI_VID_INTEL, IMC_M2MEM_DEVID, dev)))
+		pci_or_config32(dev, IMC_M2MEM_TIMEOUT, TIMEOUT_LOCK);
+}
+
+static void set_upi_locks(void)
+{
+	struct device *dev = 0;
+	while ((dev = dev_find_device(PCI_VID_INTEL, UPI_LL_CR_DEVID, dev)))
+		pci_or_config32(dev, UPI_LL_CR_KTIMISCMODLCK, KTIMISCMODLCK_LOCK);
 }
 
 static void soc_final(void *data)
 {
 	// Temp Fix - should be done by FSP, in 2S bios completion
 	// is not carried out on socket 2
+	set_pcu_locks();
+	set_imc_locks();
+	set_upi_locks();
+
 	set_bios_init_completion();
 }
 
+static void soc_init(void *data)
+{
+	printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
+	fsp_silicon_init();
+
+	setup_pds();
+	attach_iio_stacks();
+
+	override_hpet_ioapic_bdf();
+	pch_lock_dmictl();
+}
+
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 {
 	const struct microcode *microcode_file;
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index ec5215321e..e245bfb5dd 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -34,24 +34,33 @@
 
 #define PCU_IIO_STACK                   1
 #define PCU_DEV                         30
-#define PCU_CR1_FUN                     1
-#define PCU_CR1_DEVID                   0x2081
 
 #define PCU_CR0_FUN                     0
 #define PCU_CR0_DEVID                   0x2080
 #define PCU_DEV_CR0(bus)                _PCU_DEV(bus, PCU_CR0_FUN)
 #define PCU_CR0_PLATFORM_INFO           0xa8
+#define PCU_CR0_TURBO_ACTIVATION_RATIO  0xb0
+#define   TURBO_ACTIVATION_RATIO_LOCK   BIT(31)
 #define PCU_CR0_P_STATE_LIMITS          0xd8
 #define P_STATE_LIMITS_LOCK_SHIFT       31
 #define P_STATE_LIMITS_LOCK             (1 << P_STATE_LIMITS_LOCK_SHIFT)
 #define PCU_CR0_TEMPERATURE_TARGET      0xe4
 #define PCU_CR0_PACKAGE_RAPL_LIMIT      0xe8
+#define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR   (PCU_CR0_PACKAGE_RAPL_LIMIT + 4)
+#define   PKG_PWR_LIM_LOCK_UPR          BIT(31)
 #define PCU_CR0_CURRENT_CONFIG          0xf8
 #define MAX_NON_TURBO_LIM_RATIO_SHIFT   8 /* 8:15 */
 #define MAX_NON_TURBO_LIM_RATIO_MASK    (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT)
 #define PCU_CR0_PMAX                    0xf0
 #define   PMAX_LOCK                     BIT(31)
 
+#define PCU_CR1_FUN                     1
+#define PCU_CR1_DEVID                   0x2081
+
+#define PCU_CR1_C2C3TT_REG                                 0xdc
+#define PCU_CR1_PCIE_ILTR_OVRD                             0xfc
+#define PCU_CR1_SAPMCTL                                    0xb0
+
 #define PCU_CR1_BIOS_MB_DATA_REG                           0x8c
 
 #define PCU_CR1_BIOS_MB_INTERFACE_REG                      0x90
@@ -71,10 +80,39 @@
 #define   PCODE_INIT_DONE3_MASK                            BIT(11)
 #define   PCODE_INIT_DONE4_MASK                            BIT(12)
 
+#define PCU_CR1_MC_BIOS_REQ                                0x98
+
 #define PCU_CR1_DESIRED_CORES_CFG2_REG                     0xa0
 #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK           BIT(31)
 
+#define PCU_CR1_SAPMCTL                                    0xb0
+#define SAPMCTL_LOCK_MASK                                   BIT(31)
+
+#define PCU_CR2_FUN                     2
 #define PCU_CR2_DEVID                   0x2082
+#define PCU_DEV_CR2(bus)                                   _PCU_DEV(bus, PCU_CR2_FUN)
+#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK                0x8c
+#define PCIE_IN_PKGCSTATE_L1_MASK                          0xFFFFFF /* 23:0 bits */
+#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2               0x90
+#define KTI_IN_PKGCSTATE_L1_MASK                           0x7 /* 2:0 bits */
+#define PCU_CR2_DRAM_POWER_INFO_LWR                        0xa8
+#define PCU_CR2_DRAM_POWER_INFO_UPR                        (PCU_CR2_DRAM_POWER_INFO_LWR + 4)
+#define   DRAM_POWER_INFO_LOCK_UPR                         BIT(31)
+#define PCU_CR2_DYNAMIC_PERF_POWER_CTL                     0xdc
+#define UNCORE_PLIMIT_OVERRIDE_BIT                         20
+#define UNOCRE_PLIMIT_OVERRIDE_SHIFT                       (1 << UNCORE_PLIMIT_OVERRIDE_BIT)
+#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG                 0xb0
+#define PROCHOT_RATIO                                      0xa /* bits 0:7 */
+#define PCU_CR2_DRAM_PLANE_POWER_LIMIT                     0xf0
+#define PP_PWR_LIM_LOCK                                    BIT(31)
+
+#define PCU_CR3_FUN                     3
+#define PCU_CR3_DEVID                   0x2083
+#define PCU_DEV_CR3(bus)                                   _PCU_DEV(bus, PCU_CR3_FUN)
+#define PCU_CR3_CONFIG_TDP_CONTROL                         0x60
+#define   TDP_LOCK                                         BIT(31)
+#define PCU_CR3_FLEX_RATIO                                 0xa0
+#define   OC_LOCK                                          BIT(20)
 
 #if !defined(__SIMPLE_DEVICE__)
 #define _UBOX_DEV(func)		pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__)
@@ -114,24 +152,6 @@
 #define VTD_BAR_CSR			0x180
 #define VTD_LTDPR			0x290
 
-#define PCU_CR1_C2C3TT_REG                                 0xdc
-#define PCU_CR1_PCIE_ILTR_OVRD                             0xfc
-#define PCU_CR1_SAPMCTL                                    0xb0
-#define SAPMCTL_LOCK_SHIFT                                 31
-#define SAPMCTL_LOCK_MASK                                  (1 << SAPMCTL_LOCK_SHIFT)
-#define PCU_CR1_MC_BIOS_REQ                                0x98
-
-#define PCU_CR2_FUN                                        2
-#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK                0x8c
-#define PCIE_IN_PKGCSTATE_L1_MASK                          0xFFFFFF /* 23:0 bits */
-#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2               0x90
-#define KTI_IN_PKGCSTATE_L1_MASK                           0x7 /* 2:0 bits */
-#define PCU_CR2_DYNAMIC_PERF_POWER_CTL                     0xdc
-#define UNCORE_PLIMIT_OVERRIDE_BIT                         20
-#define UNOCRE_PLIMIT_OVERRIDE_SHIFT                       (1 << UNCORE_PLIMIT_OVERRIDE_BIT)
-#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG                 0xb0
-#define PROCHOT_RATIO                                      0xa /* bits 0:7 */
-
 #define CHA_UTIL_ALL_DEV                                   29
 #define CHA_UTIL_ALL_FUNC                                  1
 #define CHA_UTIL_ALL_MMCFG_CSR                             0xc0
@@ -147,6 +167,18 @@
 #define VTD_DEV(bus)		PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
 #endif
 
+/* IMC Devices */
+/* Bus: B(2), Device: 9-8, Function: 0 (M2MEM) */
+#define IMC_M2MEM_DEVID			0x2066
+#define IMC_M2MEM_TIMEOUT		0x104
+#define   TIMEOUT_LOCK			BIT(1)
+
+/* UPI Devices */
+/* Bus: B(3), Device: 16,14, Function: 3 (LL_CR) */
+#define UPI_LL_CR_DEVID			0x205B
+#define UPI_LL_CR_KTIMISCMODLCK		0x300
+#define   KTIMISCMODLCK_LOCK		BIT(0)
+
 #define CBDMA_DEV_NUM           0x04
 #define IIO_CBDMA_MMIO_SIZE     0x10000 //64kB for one CBDMA function
 #define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 9d68d445a8..2b4fa8d836 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -86,30 +86,16 @@ bool is_ubox_stack_res(const STACK_RES *res)
 #if ENV_RAMSTAGE
 void config_reset_cpl3_csrs(void)
 {
-	uint32_t data, plat_info, max_min_turbo_limit_ratio;
+	uint32_t data;
 	struct device *dev;
 
-	dev = NULL;
-	while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) {
-		data = pci_read_config32(dev, PCU_CR0_P_STATE_LIMITS);
-		data |= P_STATE_LIMITS_LOCK;
-		pci_write_config32(dev, PCU_CR0_P_STATE_LIMITS, data);
-
-		plat_info = pci_read_config32(dev, PCU_CR0_PLATFORM_INFO);
-		dump_csr64(dev, PCU_CR0_PLATFORM_INFO);
-		max_min_turbo_limit_ratio =
-			(plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
-				MAX_NON_TURBO_LIM_RATIO_SHIFT;
-		printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
-			plat_info, max_min_turbo_limit_ratio);
-	}
+	// FIXME: Looks like this needs to run after FSP-S since it modifies FSP defaults!
 
 	dev = NULL;
 	while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) {
 		data = pci_read_config32(dev, PCU_CR1_SAPMCTL);
 		/* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
 		data &= 0x0fffffff;
-		data |= SAPMCTL_LOCK_MASK;
 		pci_write_config32(dev, PCU_CR1_SAPMCTL, data);
 	}