diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2023-03-29 20:14:11 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-07 13:28:01 +0000 |
| commit | 64d2fd0777125806f49408f4906fd63eea6d3e16 (patch) | |
| tree | 7aca826017892971bdeb4e19718efb721ffa94e0 /src/soc/intel/xeon_sp | |
| parent | 04fde7ed374bb0811f6d27a07104a03a421a3dd1 (diff) | |
soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms
NUMA will be supported by SPR and future generations.
TEST=intel/archercity CRB
Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/Makefile.mk | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/numa.c (renamed from src/soc/intel/xeon_sp/spr/numa.c) | 0 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Makefile.mk | 2 |
5 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 59335a1c41..52aaec1797 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -106,4 +106,7 @@ config SOC_INTEL_XEON_RAS config HAVE_IOAT_DOMAINS bool +config SOC_INTEL_HAS_CXL + bool + endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index a732c78b53..58915447b7 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -13,7 +13,7 @@ ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c -ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c +ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += smihandler.c pmutil.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/spr/numa.c b/src/soc/intel/xeon_sp/numa.c index 23f52c625f..23f52c625f 100644 --- a/src/soc/intel/xeon_sp/spr/numa.c +++ b/src/soc/intel/xeon_sp/numa.c diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index acc5e4a1b9..3c3c45ace4 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -15,6 +15,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP select HAVE_IOAT_DOMAINS select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING + select SOC_INTEL_HAS_CXL help Intel Sapphire Rapids-SP support @@ -114,9 +115,6 @@ config SOC_INTEL_HAS_BIOS_DONE_MSR config SOC_INTEL_HAS_NCMEM def_bool y -config SOC_INTEL_HAS_CXL - def_bool y - config SOC_INTEL_PCIE_64BIT_ALLOC def_bool y diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 659e366b4b..163b5ea94d 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -12,7 +12,7 @@ romstage-y += romstage.c soc_util.c ddr.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c numa.c reset.c +ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c xhci.c reset.c ramstage-y += crashlog.c ioat.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c |