diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-10 12:38:02 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 20:21:45 +0000 |
| commit | 34f26b298961300fe97234ac5f424f57ebd04aad (patch) | |
| tree | 9221a4e220dfacee5ecda62ee216104416933e74 /src/soc/intel/xeon_sp | |
| parent | 03c0853f4d58c73a632f81cac2eb16b759d7f338 (diff) | |
drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.
For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.
Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
Additionally, fixed SoC configs inclusion order alphabetically.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 31 |
1 files changed, 17 insertions, 14 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 32c2380216..d8c6a3911b 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -26,18 +26,26 @@ if XEON_SP_COMMON_BASE config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_RESET + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_CAR + select FSP_M_XIP select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP - select FSP_M_XIP - select POSTCAR_STAGE + select HAVE_SMI_HANDLER + select INTEL_CAR_NEM # For postcar only now + select INTEL_DESCRIPTOR_MODE_CAPABLE + select NO_FSP_TEMP_RAM_EXIT select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK - select INTEL_DESCRIPTOR_MODE_CAPABLE + select POSTCAR_STAGE + select REG_SCRIPT + select SMM_TSEG + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT @@ -47,18 +55,13 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_SERVER + select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT select UDELAY_TSC - select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select FSP_CAR - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SMM_TSEG - select HAVE_SMI_HANDLER - select REG_SCRIPT - select NO_FSP_TEMP_RAM_EXIT - select INTEL_CAR_NEM # For postcar only now + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config MAINBOARD_USES_FSP2_0 bool |