diff options
| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-12-16 08:45:53 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-15 02:29:51 +0000 |
| commit | 8e4500aa57afd856aa7f0acc57d8e5ba68fea90a (patch) | |
| tree | d497223f6dc03187793277f0957d4d257c4f146d /src/soc/intel/xeon_sp/util.c | |
| parent | ef1297689d8c12ca6db2c9295bcb6974e6b4e423 (diff) | |
soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOAD
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL
MSR at a late BS_PAYLOAD_LOAD boot state.
This MSR is in platform scope and must only be locked once on each
socket. Add a spinlock to do so.
Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/util.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/util.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 0c8e63a640..525efc5add 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -68,9 +68,6 @@ msr_t read_msr_ppin(void) wrmsr(MSR_PPIN_CTL, msr); } ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); return ppin; } |