diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-05-16 06:13:10 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-10-02 13:51:22 +0000 |
| commit | 1bebdc0d72516706768ef4752e0a1d953e3639db (patch) | |
| tree | e00f0e2936e7967d942faa960c4d0711710f653a /src/soc/intel/xeon_sp/uncore.c | |
| parent | bc853b72aca27aba3431be9775373755ea9b6435 (diff) | |
soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resources
On GNR, there are CXL Type-3 memory windows covered under TOHM. The
current 4GB to TOHM DRAM reporting doesn't work on GNR.
Use MemoryMapDataHob to add high RAM resources as a generic
mechanism for GNR and previous generation SoCs.
TEST=Build and boot on intel/archercity CRB
TEST=Build and boot on intel/beechnutcity CRB
(with topic:"Xeon6-Basic-Boot")
Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/uncore.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index be5b38f9c3..c20e55fdce 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -284,21 +284,25 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) mc_values[TOLM_REG]); LOG_RESOURCE("mmio_tolm", dev, res); - if (CONFIG(SOC_INTEL_HAS_CXL)) { - /* 4GiB -> CXL Memory */ - uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ - /* - * Memory layout when there is CXL HDM (Host-managed Device Memory): - * -------------- <- TOHM - * CXL memory regions (pds global variable records the base/size of them) - * Processor attached high memory - * -------------- <- 0x100000000 (4GB) - */ - res = upper_ram_end(dev, index++, - mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); + /* Add high RAM */ + const struct SystemMemoryMapHob *mm = get_system_memory_map(); + + for (int i = 0; i < mm->numberEntries; i++) { + const struct SystemMemoryMapElement *e = &mm->Element[i]; + uint64_t addr = ((uint64_t)e->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = ((uint64_t)e->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); + if (addr < 4ULL * GiB) + continue; + if (!is_memtype_processor_attached(e->Type)) + continue; + if (is_memtype_reserved(e->Type)) + continue; + + res = ram_range(dev, index++, addr, size); LOG_RESOURCE("high_ram", dev, res); + } + if (CONFIG(SOC_INTEL_HAS_CXL)) { /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { @@ -320,10 +324,6 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) else LOG_RESOURCE("CXL_memory", dev, res); } - } else { - /* 4GiB -> TOHM */ - res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1); - LOG_RESOURCE("high_ram", dev, res); } /* add MMIO CFG resource */ |