diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-04-26 17:35:05 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-02 17:43:42 +0000 |
| commit | a0aff6e15988f918b926c4cd222537d2f5a3f878 (patch) | |
| tree | 593424f7bba43c6b2361f305334c3ac8eac3f6e1 /src/soc/intel/xeon_sp/spr | |
| parent | b25fa1cf9ee3ea51c4c183d2d7f3d79c0bf8d573 (diff) | |
soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 3e16608ca4..39f46ffc17 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -13,12 +13,14 @@ #include <fsp/util.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/soc_pch.h> #include <soc/intel/common/smbios.h> #include <string.h> #include <soc/soc_util.h> +#include <soc/util.h> #include <soc/ddr.h> #include "chip.h" @@ -39,7 +41,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd) static void config_upd_from_vpd(FSPM_UPD *mupd) { uint8_t val; - int val_int, cxl_mode; + int val_int; /* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) @@ -97,8 +99,8 @@ static void config_upd_from_vpd(FSPM_UPD *mupd) mupd->FspmConfig.DfxPmicSecureMode = FSP_PMIC_SECURE_MODE_DEFAULT; } - cxl_mode = get_cxl_mode_from_vpd(); - if (cxl_mode == CXL_SYSTEM_MEMORY || cxl_mode == CXL_SPM) + int cxl_mode = get_cxl_mode(); + if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM) mupd->FspmConfig.DfxCxlType3LegacyEn = 1; else /* Disable CXL */ mupd->FspmConfig.DfxCxlType3LegacyEn = 0; |